JPH0415858U - - Google Patents
Info
- Publication number
- JPH0415858U JPH0415858U JP1990056749U JP5674990U JPH0415858U JP H0415858 U JPH0415858 U JP H0415858U JP 1990056749 U JP1990056749 U JP 1990056749U JP 5674990 U JP5674990 U JP 5674990U JP H0415858 U JPH0415858 U JP H0415858U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- lead frame
- element fixed
- hybrid integrated
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims 1
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第1図a,b及び第2図はa,bは本考案の第
1及び第2の実施例を説明するための平面図及び
断面図、第3図a,bは従来の混成集積回路の平
面図及び断面図である。
1……リードフレーム、2……接着剤、3……
絶縁樹脂、4……配線パターン、5……マウント
樹脂、6A,6B……半導体素子、7……ワイヤ
ー。
1A and 2B are plan views and cross-sectional views for explaining the first and second embodiments of the present invention, and FIGS. 3A and 3B are views of conventional hybrid integrated circuits. They are a plan view and a sectional view. 1... Lead frame, 2... Adhesive, 3...
Insulating resin, 4... Wiring pattern, 5... Mounting resin, 6A, 6B... Semiconductor element, 7... Wire.
Claims (1)
前記リードフレーム上に絶縁基板を介して固着さ
れた半導体素子とを含むことを特徴とする混成集
積回路。 A semiconductor element fixed on a lead frame,
A hybrid integrated circuit comprising: a semiconductor element fixed on the lead frame via an insulating substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1990056749U JPH0415858U (en) | 1990-05-30 | 1990-05-30 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1990056749U JPH0415858U (en) | 1990-05-30 | 1990-05-30 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0415858U true JPH0415858U (en) | 1992-02-07 |
Family
ID=31580853
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1990056749U Pending JPH0415858U (en) | 1990-05-30 | 1990-05-30 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0415858U (en) |
-
1990
- 1990-05-30 JP JP1990056749U patent/JPH0415858U/ja active Pending