JPS61140574U - - Google Patents
Info
- Publication number
- JPS61140574U JPS61140574U JP2284685U JP2284685U JPS61140574U JP S61140574 U JPS61140574 U JP S61140574U JP 2284685 U JP2284685 U JP 2284685U JP 2284685 U JP2284685 U JP 2284685U JP S61140574 U JPS61140574 U JP S61140574U
- Authority
- JP
- Japan
- Prior art keywords
- hybrid integrated
- integrated circuit
- metal film
- package
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 2
- 229920003002 synthetic resin Polymers 0.000 claims 1
- 239000000057 synthetic resin Substances 0.000 claims 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
Landscapes
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Casings For Electric Apparatus (AREA)
Description
第１図は本考案に依る混成集積回路の構造を示
す斜視図、第２図は従来従術に依る混成集積回路
の構造の一例を示す斜視図である。
図に於いて、１，１′は混成集積回路、２は基
板、３は導体、４はチツプ素子、５はリード線、
６はパツケージング、７は金属皮膜、８は絶縁皮
膜、９はアース用リード線である。
FIG. 1 is a perspective view showing the structure of a hybrid integrated circuit according to the present invention, and FIG. 2 is a perspective view showing an example of the structure of a conventional hybrid integrated circuit. In the figure, 1 and 1' are hybrid integrated circuits, 2 is a substrate, 3 is a conductor, 4 is a chip element, 5 is a lead wire,
6 is packaging, 7 is a metal film, 8 is an insulating film, and 9 is a grounding lead wire.
Claims (1)
体を合成樹脂で固めてパツケージを固めてパツケ
ージングを行つた混成集積回路装置であつて、ア
ース用リード線を有して前記パツケージの全体を
覆う金属皮膜と、前記金属皮膜の全体とを有する
ことを特徴とする混成集積回路装置。 This is a hybrid integrated circuit device in which active elements forming a circuit are mounted on a substrate, and the entire package is hardened with synthetic resin to form a package. A hybrid integrated circuit device comprising a covering metal film and the entire metal film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2284685U JPS61140574U (en) | 1985-02-20 | 1985-02-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2284685U JPS61140574U (en) | 1985-02-20 | 1985-02-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61140574U true JPS61140574U (en) | 1986-08-30 |
Family
ID=30515526
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2284685U Pending JPS61140574U (en) | 1985-02-20 | 1985-02-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61140574U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6471312A (en) * | 1987-09-11 | 1989-03-16 | Murata Manufacturing Co | Resonator |
-
1985
- 1985-02-20 JP JP2284685U patent/JPS61140574U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6471312A (en) * | 1987-09-11 | 1989-03-16 | Murata Manufacturing Co | Resonator |