JPS63157973U - - Google Patents
Info
- Publication number
- JPS63157973U JPS63157973U JP5022187U JP5022187U JPS63157973U JP S63157973 U JPS63157973 U JP S63157973U JP 5022187 U JP5022187 U JP 5022187U JP 5022187 U JP5022187 U JP 5022187U JP S63157973 U JPS63157973 U JP S63157973U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit device
- hybrid integrated
- resin film
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000008188 pellet Substances 0.000 claims description 2
- 230000001681 protective effect Effects 0.000 claims description 2
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 239000004020 conductor Substances 0.000 description 1
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
第１図は本考案の一実施例を説明するための混
成集積回路装置の断面図、第２図は従来の一例を
説明するための混成集積回路装置の断面図である
。
１……絶縁性基板、２……導体パターン、３…
…半導体ペレツト、４……Ａｇペースト、５……
Ａｕ線、６……保護樹脂膜、７……半導体素子。
FIG. 1 is a cross-sectional view of a hybrid integrated circuit device for explaining an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a hybrid integrated circuit device for explaining a conventional example. 1... Insulating substrate, 2... Conductor pattern, 3...
...Semiconductor pellet, 4...Ag paste, 5...
Au wire, 6... protective resin film, 7... semiconductor element.
Claims (1)
に於いて、絶縁性基板に搭載し保護樹脂膜でコー
テイングした半導体ペレツトの上に位置するよう
にパツケージされた半導体素子を搭載することを
特徴とする混成集積回路装置。 A hybrid integrated circuit device equipped with a plurality of active elements is characterized in that a packaged semiconductor element is mounted so as to be positioned on a semiconductor pellet mounted on an insulating substrate and coated with a protective resin film. Hybrid integrated circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5022187U JPS63157973U (en) | 1987-04-01 | 1987-04-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5022187U JPS63157973U (en) | 1987-04-01 | 1987-04-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63157973U true JPS63157973U (en) | 1988-10-17 |
Family
ID=30873380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5022187U Pending JPS63157973U (en) | 1987-04-01 | 1987-04-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63157973U (en) |
-
1987
- 1987-04-01 JP JP5022187U patent/JPS63157973U/ja active Pending