JPS62104452U - - Google Patents
Info
- Publication number
- JPS62104452U JPS62104452U JP19809985U JP19809985U JPS62104452U JP S62104452 U JPS62104452 U JP S62104452U JP 19809985 U JP19809985 U JP 19809985U JP 19809985 U JP19809985 U JP 19809985U JP S62104452 U JPS62104452 U JP S62104452U
- Authority
- JP
- Japan
- Prior art keywords
- chip carrier
- integrated circuit
- hybrid integrated
- ceramic substrate
- insulating pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Description
第１図は本考案のハイブリツド集積回路の実装
図、第２図は第１図の断面図、第３図は従来のハ
イブリツド集積回路の実装図、第４図は第３図の
断面図、第５図は異常時の状態図である。
１……セラミツク基板、２……チツプキヤリア
、３……パツド、４……半田、５……チツプキヤ
リア端子、６……コーテイング、７……絶縁パタ
ーン。
Fig. 1 is a mounting diagram of the hybrid integrated circuit of the present invention, Fig. 2 is a sectional view of Fig. 1, Fig. 3 is a mounting diagram of a conventional hybrid integrated circuit, and Fig. 4 is a sectional view of Fig. 3, and Fig. 4 is a sectional view of Fig. 3. FIG. 5 is a state diagram at the time of abnormality. 1... Ceramic substrate, 2... Chip carrier, 3... Pad, 4... Solder, 5... Chip carrier terminal, 6... Coating, 7... Insulating pattern.
Claims (1)
その周囲をコーテイング材で被覆してなるハイブ
リツド集積回路において、チツプキヤリアの端子
間を絶縁パターンにて隔離したことを特徴とする
ハイブリツド集積回路。 A chip carrier is mounted on a ceramic substrate,
A hybrid integrated circuit whose periphery is covered with a coating material, characterized in that terminals of a chip carrier are isolated by an insulating pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19809985U JPS62104452U (en) | 1985-12-23 | 1985-12-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19809985U JPS62104452U (en) | 1985-12-23 | 1985-12-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62104452U true JPS62104452U (en) | 1987-07-03 |
Family
ID=31158475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19809985U Pending JPS62104452U (en) | 1985-12-23 | 1985-12-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62104452U (en) |
-
1985
- 1985-12-23 JP JP19809985U patent/JPS62104452U/ja active Pending