JPS6226050U - - Google Patents
Info
- Publication number
- JPS6226050U JPS6226050U JP11774185U JP11774185U JPS6226050U JP S6226050 U JPS6226050 U JP S6226050U JP 11774185 U JP11774185 U JP 11774185U JP 11774185 U JP11774185 U JP 11774185U JP S6226050 U JPS6226050 U JP S6226050U
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- plate capacitor
- film substrate
- package
- land
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 claims description 9
- 239000003990 capacitor Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
Description
第１図は本考案の薄膜混成集積回路の一実施例
の縦断面図、第２図は、第１図に示したランド８
を有する単板コンデンサ２の平面図、第３図は薄
膜混成集積回路の従来例の断面図である。
１…パツケージ、２…単板コンデンサ、３…薄
膜基板、４…絶縁性接着剤、５…電子部品、６…
パツケージ１の端子ピン、７…ボンデイングワイ
ヤ、８…単板コンデンサ２のランド。
FIG. 1 is a longitudinal sectional view of an embodiment of the thin film hybrid integrated circuit of the present invention, and FIG. 2 is a land 8 shown in FIG. 1.
FIG. 3 is a sectional view of a conventional example of a thin film hybrid integrated circuit. DESCRIPTION OF SYMBOLS 1...Package cage, 2...Single plate capacitor, 3...Thin film substrate, 4...Insulating adhesive, 5...Electronic component, 6...
Terminal pin of package 1, 7... bonding wire, 8... land of single plate capacitor 2.
Claims (1)
あつて、 前記パツケージ上に搭載されたマルチランドを
有する単板コンデンサと、 前記単板コンデンサ上に絶縁性接着剤を介して
搭載され、前記単板コンデンサに比べて小さい薄
膜基板と、 前記薄膜基板に搭載された電子部品と、 前記パツケージの端子ピンと前記単板コンデン
サのランドと前記薄膜基板を接続するボンデイン
グワイヤを有する薄膜混成集積回路。[Claims for Utility Model Registration] A thin film hybrid integrated circuit constructed on a package, comprising: a single-plate capacitor having a multi-land mounted on the package; and an insulating adhesive on the single-plate capacitor. a thin film substrate that is mounted on a thin film substrate and is smaller than the single plate capacitor; an electronic component mounted on the thin film substrate; and a thin film that has a bonding wire that connects the terminal pin of the package, the land of the single plate capacitor, and the thin film substrate. Hybrid integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11774185U JPS6226050U (en) | 1985-07-31 | 1985-07-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11774185U JPS6226050U (en) | 1985-07-31 | 1985-07-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6226050U true JPS6226050U (en) | 1987-02-17 |
Family
ID=31003536
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11774185U Pending JPS6226050U (en) | 1985-07-31 | 1985-07-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6226050U (en) |
-
1985
- 1985-07-31 JP JP11774185U patent/JPS6226050U/ja active Pending
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