JPS6418751U - - Google Patents

Info

Publication number
JPS6418751U
JPS6418751U JP11341687U JP11341687U JPS6418751U JP S6418751 U JPS6418751 U JP S6418751U JP 11341687 U JP11341687 U JP 11341687U JP 11341687 U JP11341687 U JP 11341687U JP S6418751 U JPS6418751 U JP S6418751U
Authority
JP
Japan
Prior art keywords
metal substrate
integrated circuit
lead
hybrid integrated
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11341687U
Other languages
Japanese (ja)
Other versions
JPH0440283Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11341687U priority Critical patent/JPH0440283Y2/ja
Publication of JPS6418751U publication Critical patent/JPS6418751U/ja
Application granted granted Critical
Publication of JPH0440283Y2 publication Critical patent/JPH0440283Y2/ja
Expired legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第4図は本考案の一実施例を説明す
るための図、第5図乃至第8図は本考案の他の一
実施例を説明するための図、第9図及び第10図
は従来の混成集積回路用リードを説明するための
図である。 1……混成集積回路用リード、2……端子ピン
、3……連結部、4……固定部、5……金属基板
、6……絶縁皮膜、7……電子部品、8……混成
集積回路、9……端子部。
Figures 1 to 4 are diagrams for explaining one embodiment of the present invention, Figures 5 to 8 are diagrams for explaining another embodiment of the present invention, and Figures 9 and 10 are diagrams for explaining another embodiment of the present invention. The figure is a diagram for explaining a conventional lead for a hybrid integrated circuit. DESCRIPTION OF SYMBOLS 1... Lead for hybrid integrated circuit, 2... Terminal pin, 3... Connecting part, 4... Fixing part, 5... Metal substrate, 6... Insulating film, 7... Electronic component, 8... Hybrid integration Circuit, 9... terminal section.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 一方の面に絶縁皮膜の形成された金属基板に接
続される混成集積回路用リードにおいて、上記金
属基板の両面を挟持するように構成されているこ
とを特徴とする混成集積回路用リード。
1. A hybrid integrated circuit lead connected to a metal substrate having an insulating film formed on one surface thereof, the lead being configured to sandwich both surfaces of the metal substrate.
JP11341687U 1987-07-24 1987-07-24 Expired JPH0440283Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11341687U JPH0440283Y2 (en) 1987-07-24 1987-07-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11341687U JPH0440283Y2 (en) 1987-07-24 1987-07-24

Publications (2)

Publication Number Publication Date
JPS6418751U true JPS6418751U (en) 1989-01-30
JPH0440283Y2 JPH0440283Y2 (en) 1992-09-21

Family

ID=31353231

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11341687U Expired JPH0440283Y2 (en) 1987-07-24 1987-07-24

Country Status (1)

Country Link
JP (1) JPH0440283Y2 (en)

Also Published As

Publication number Publication date
JPH0440283Y2 (en) 1992-09-21

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