JPS61149334U - - Google Patents
Info
- Publication number
- JPS61149334U JPS61149334U JP3103885U JP3103885U JPS61149334U JP S61149334 U JPS61149334 U JP S61149334U JP 3103885 U JP3103885 U JP 3103885U JP 3103885 U JP3103885 U JP 3103885U JP S61149334 U JPS61149334 U JP S61149334U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- circuit
- recess
- hybrid integrated
- circuit components
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Description
第１図はこの考案による混成集積回路装置の実
施例を示す断面図、第２図は従来の混成集積回路
装置の例を示す断面図である。
図において、１は基板、２は導体、３は部品用
電極、４は回路部品、５は導電性接着剤、６はワ
イヤ、７は凹部である。なお、各図中同一符号は
同一または相当部分を示す。
FIG. 1 is a sectional view showing an embodiment of a hybrid integrated circuit device according to this invention, and FIG. 2 is a sectional view showing an example of a conventional hybrid integrated circuit device. In the figure, 1 is a substrate, 2 is a conductor, 3 is an electrode for a component, 4 is a circuit component, 5 is a conductive adhesive, 6 is a wire, and 7 is a recessed portion. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
混成集積回路装置においてサブストレートを形成
する基板の上記回路部品を搭載しようとする部分
を回路部品の形状に応じた凹部に形成し、その凹
部中に回路部品を固着したことを特徴とする混成
集積回路装置。 In a hybrid integrated circuit device in which an electronic circuit is configured by mounting circuit components on a substrate, a portion of the substrate forming the substrate on which the circuit components are to be mounted is formed into a recess corresponding to the shape of the circuit component, and a recess is formed in the recess. A hybrid integrated circuit device characterized by having circuit components fixed to it.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3103885U JPS61149334U (en) | 1985-03-05 | 1985-03-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3103885U JPS61149334U (en) | 1985-03-05 | 1985-03-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61149334U true JPS61149334U (en) | 1986-09-16 |
Family
ID=30531279
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3103885U Pending JPS61149334U (en) | 1985-03-05 | 1985-03-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61149334U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010073994A (en) * | 2008-09-19 | 2010-04-02 | Powertech Technology Inc | Window type bga package and manufacturing method thereof |
-
1985
- 1985-03-05 JP JP3103885U patent/JPS61149334U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010073994A (en) * | 2008-09-19 | 2010-04-02 | Powertech Technology Inc | Window type bga package and manufacturing method thereof |