JPS6183073U - - Google Patents
Info
- Publication number
- JPS6183073U JPS6183073U JP1984168711U JP16871184U JPS6183073U JP S6183073 U JPS6183073 U JP S6183073U JP 1984168711 U JP1984168711 U JP 1984168711U JP 16871184 U JP16871184 U JP 16871184U JP S6183073 U JPS6183073 U JP S6183073U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- chamfered
- integrated circuit
- hybrid integrated
- end surfaces
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 4
Landscapes
- Multi-Conductor Connections (AREA)
- Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
第１図はこの考案による混成集積回路用基板の
実施例を示す断面図、第２図、第３図、第４図お
よび第５図はそれぞれ従来の混成集積回路用基板
の例を示す断面図である。
図において、１は基板、２は側端面導体、３，
４それぞれ導体、６は面取りした面である。なお
、各図中同一または相当部分を示す。
FIG. 1 is a sectional view showing an embodiment of a hybrid integrated circuit board according to this invention, and FIGS. 2, 3, 4, and 5 are sectional views showing examples of conventional hybrid integrated circuit boards, respectively. It is. In the figure, 1 is a substrate, 2 is a side end surface conductor, 3,
4 is a conductor, and 6 is a chamfered surface. Note that the same or corresponding parts are shown in each figure.
Claims (1)
の側端面を所定の角度で面取りするとともに、そ
の面取りした側端面に設けた導体と基板の一方の
面および他方の面に設けた導体とが上記の面取り
部分において互に部分的に重なり合うように形成
したことを特徴とする混成集積回路用基板。 The side end surfaces of the substrate forming the substrate of the hybrid integrated circuit are chamfered at a predetermined angle, and the conductors provided on the chamfered side end surfaces and the conductors provided on one side and the other side of the substrate are chamfered as described above. 1. A hybrid integrated circuit substrate, characterized in that the substrate is formed so that the parts thereof partially overlap each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984168711U JPS6183073U (en) | 1984-11-07 | 1984-11-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984168711U JPS6183073U (en) | 1984-11-07 | 1984-11-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6183073U true JPS6183073U (en) | 1986-06-02 |
Family
ID=30726472
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984168711U Pending JPS6183073U (en) | 1984-11-07 | 1984-11-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6183073U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03225990A (en) * | 1990-01-31 | 1991-10-04 | Hitachi Ltd | Method and apparatus for manufacture of wiring board |
-
1984
- 1984-11-07 JP JP1984168711U patent/JPS6183073U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03225990A (en) * | 1990-01-31 | 1991-10-04 | Hitachi Ltd | Method and apparatus for manufacture of wiring board |