JPS5948070U - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPS5948070U JPS5948070U JP14383282U JP14383282U JPS5948070U JP S5948070 U JPS5948070 U JP S5948070U JP 14383282 U JP14383282 U JP 14383282U JP 14383282 U JP14383282 U JP 14383282U JP S5948070 U JPS5948070 U JP S5948070U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- dielectric substrate
- hybrid integrated
- circuit device
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の混成集積回路装置の構造を示す断面側面
図、第２図は第１図に示す混成集積回路装置のハンダ付
は組立後の状態を示す断面側面図、第３図は本考案の一
実施例による混成集積回路装置め誘電体基板の底面図、
第４図は上記実施例装置の断面側面図、第５図は本考案
の他の実施例の誘電体基板の底面図である。
１・・・誘電体基板、２・・・金属製フランジ、３．３
′・・・ハンダ、４．４′・・・金属層、６・・・電気
的絶縁材料。。Figure 1 is a cross-sectional side view showing the structure of a conventional hybrid integrated circuit device, Figure 2 is a cross-sectional side view showing the soldering state of the hybrid integrated circuit device shown in Figure 1 after assembly, and Figure 3 is a cross-sectional side view showing the soldering state of the hybrid integrated circuit device shown in Figure 1. A bottom view of a dielectric substrate for a hybrid integrated circuit device according to an embodiment of the invention,
FIG. 4 is a cross-sectional side view of the device of the above embodiment, and FIG. 5 is a bottom view of a dielectric substrate of another embodiment of the present invention. 1... Dielectric substrate, 2... Metal flange, 3.3
'...Solder, 4.4'...Metal layer, 6...Electrical insulating material. .
Claims (3)
と、該誘電体基板の裏面の中心部にメタライズにより形
成された薄い金属層と、上記誘電体基板を固着すべき金
属製フランジと、上記誘電体基板をその裏面の金属層部
分で上記金属製フランジにハンダ付けするハンダとを備
えたことを特徴とする混成集積回路装置。(1) A dielectric substrate with a hybrid integrated circuit formed on its surface, a thin metal layer formed by metallization at the center of the back surface of the dielectric substrate, and a metal flange to which the dielectric substrate is fixed. and a solder for soldering the dielectric substrate to the metal flange at a metal layer portion on the back surface of the dielectric substrate.
部のみに形成されていることを特徴とする実用新案登録
請求の範囲第１項記載の混成集積回路装置。(2) The hybrid integrated circuit device according to claim 1, wherein the thin metal layer is formed only at the center of the back surface of the dielectric substrate.
形成され、該薄い金属層の中心部のみが上記金属製フラ
ンジにハンダ付けされ、その周辺部が電気的絶縁材料で
被覆されていることを特徴とする実用新案登録請求の範
囲第１項記載の混成集積回路装置。(3) The thin metal layer is formed on the entire back surface of the dielectric substrate, only the center part of the thin metal layer is soldered to the metal flange, and the peripheral part is covered with an electrically insulating material. A hybrid integrated circuit device according to claim 1, characterized in that the hybrid integrated circuit device is characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14383282U JPS5948070U (en) | 1982-09-20 | 1982-09-20 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14383282U JPS5948070U (en) | 1982-09-20 | 1982-09-20 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5948070U true JPS5948070U (en) | 1984-03-30 |
Family
ID=30320930
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14383282U Pending JPS5948070U (en) | 1982-09-20 | 1982-09-20 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5948070U (en) |
-
1982
- 1982-09-20 JP JP14383282U patent/JPS5948070U/en active Pending
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