JPS5998692U - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPS5998692U JPS5998692U JP19297182U JP19297182U JPS5998692U JP S5998692 U JPS5998692 U JP S5998692U JP 19297182 U JP19297182 U JP 19297182U JP 19297182 U JP19297182 U JP 19297182U JP S5998692 U JPS5998692 U JP S5998692U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit device
- hybrid integrated
- metal plate
- insulated substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Combinations Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図及び第２図は、従来の混成集積回路の実施例あ断
面図、第３図及び第４図は、金属薄板を凹凸にした実施
例の斜視図、第５図は、三の考案装置の実施例の断面図
である。 ゛１：アルミナ基板、２：外装
容器の１部となる銅板、３：搭載部品、４：はんだ、５
：裏面導体、６：金属薄板。Figures 1 and 2 are cross-sectional views of an example of a conventional hybrid integrated circuit, Figures 3 and 4 are perspective views of an example in which a thin metal plate is made uneven, and Figure 5 is a third idea. 1 is a cross-sectional view of an embodiment of the device; FIG.゛1: Alumina substrate, 2: Copper plate that becomes part of the outer container, 3: Mounted components, 4: Solder, 5
: Back conductor, 6: Metal thin plate.
Claims (1)
板の裏面に形成した導体層と、外装容器の一部である金
属板と、該金属板と前記絶縁基板裏面導体との間にはん
だを介して接着した前記絶縁基板と、はぼ等しい線膨張
係数でかつ凹凸に形成した薄い金属板より成ることを特
徴とする混成集積回路装置。An insulated substrate on which an electronic circuit is formed, a conductive layer formed on the back side of the insulated substrate, a metal plate that is a part of the outer container, and solder between the metal plate and the conductor on the back side of the insulated substrate. 1. A hybrid integrated circuit device comprising a thin metal plate having approximately the same coefficient of linear expansion as the insulating substrate bonded to the insulating substrate via a wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19297182U JPS5998692U (en) | 1982-12-22 | 1982-12-22 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19297182U JPS5998692U (en) | 1982-12-22 | 1982-12-22 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5998692U true JPS5998692U (en) | 1984-07-04 |
Family
ID=30415148
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19297182U Pending JPS5998692U (en) | 1982-12-22 | 1982-12-22 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5998692U (en) |
-
1982
- 1982-12-22 JP JP19297182U patent/JPS5998692U/en active Pending
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