JPS58120647U - hybrid integrated circuit - Google Patents
hybrid integrated circuitInfo
- Publication number
- JPS58120647U JPS58120647U JP1982016196U JP1619682U JPS58120647U JP S58120647 U JPS58120647 U JP S58120647U JP 1982016196 U JP1982016196 U JP 1982016196U JP 1619682 U JP1619682 U JP 1619682U JP S58120647 U JPS58120647 U JP S58120647U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- semiconductor chip
- conductor land
- predetermined conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の高出力混成集積回路を示す断面図、第２
図は本考案の一実施例による高出力混成集積回路を示し
、ａは断面図、ｂは平面図を示す。
１・・・・・・絶縁性基板、２・・・・・・半導体チッ
プ搭載用導体ランド、３・・・・・・ボンディング用導
体ランド、４・・・・・・半導体チップ、５・・・・・
・ヒートスプレッダ、６．７・・・・・・ソルダ、２′
・・・・・・膜厚を厚くした半導体チップ搭載用導体ラ
ンド。Figure 1 is a cross-sectional view of a conventional high-power hybrid integrated circuit;
The figure shows a high-power hybrid integrated circuit according to an embodiment of the present invention, in which a is a cross-sectional view and b is a plan view. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Conductor land for semiconductor chip mounting, 3... Conductor land for bonding, 4... Semiconductor chip, 5... ...
・Heat spreader, 6.7...Solder, 2'
・・・・・・Conductor land for mounting semiconductor chips with thick film thickness.
Claims (1)
た混成集積回路において、少な（とも前記半導体チップ
が搭載される所定の導体ランドは残りの導体パターンに
比べて膜厚が厚いことを特徴とする混成集積回路。In a hybrid integrated circuit in which a semiconductor chip is mounted on a predetermined conductor land of a circuit board, the predetermined conductor land on which the semiconductor chip is mounted is thicker than the remaining conductor patterns. Hybrid integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982016196U JPS58120647U (en) | 1982-02-08 | 1982-02-08 | hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982016196U JPS58120647U (en) | 1982-02-08 | 1982-02-08 | hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58120647U true JPS58120647U (en) | 1983-08-17 |
Family
ID=30028573
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1982016196U Pending JPS58120647U (en) | 1982-02-08 | 1982-02-08 | hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58120647U (en) |
-
1982
- 1982-02-08 JP JP1982016196U patent/JPS58120647U/en active Pending
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