JPS587337U - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPS587337U
JPS587337U JP1981101013U JP10101381U JPS587337U JP S587337 U JPS587337 U JP S587337U JP 1981101013 U JP1981101013 U JP 1981101013U JP 10101381 U JP10101381 U JP 10101381U JP S587337 U JPS587337 U JP S587337U
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
circuit device
semiconductor chip
dissipating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1981101013U
Other languages
Japanese (ja)
Inventor
川上　隆由
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP1981101013U priority Critical patent/JPS587337U/en
Publication of JPS587337U publication Critical patent/JPS587337U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の混成集積回路装置の一例を示し、同図Ａ
は平面図、同図Ｂは断面図である。第２図はこの考案に
よる混成集積回路装置の一実施例を示し、同図Ａは平面
図、同図Ｂは断面図である。 図において、１は半導体チップ、２ａは混成集積回路基
板、２１ａは絶縁性基板、２２ａは導体層、３は接着剤
、８は放熱性基板、−９は接着剤である。 なお、図中同一符号はそれ夕゛れ同一または相当部分を
示す。Figure 1 shows an example of a conventional hybrid integrated circuit device.
is a plan view, and B is a cross-sectional view. FIG. 2 shows an embodiment of a hybrid integrated circuit device according to this invention, in which FIG. 2A is a plan view and FIG. 2B is a sectional view. In the figure, 1 is a semiconductor chip, 2a is a hybrid integrated circuit board, 21a is an insulating substrate, 22a is a conductive layer, 3 is an adhesive, 8 is a heat dissipating substrate, and -9 is an adhesive. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] （１）熱伝導性の良好な放熱性基板、この放熱性基板上
に直接に取り付けられた半導体チップ、および絶縁性基
板とこの絶縁性基板の表面上に所定のパターンに形成さ
れた導体層とからなり上記放熱性基板の半導体チップ取
付部分に対応する部分に開口部を有しこの開口部と上記
半導体チップとを位置合わせして上記放熱性基板上に取
り付けられた混成集積回路基板を備えた混成集積回路装
置。(1) A heat-dissipating substrate with good thermal conductivity, a semiconductor chip mounted directly on the heat-dissipating substrate, an insulating substrate, and a conductor layer formed in a predetermined pattern on the surface of the insulating substrate. A hybrid integrated circuit board comprising: an opening in a portion corresponding to the semiconductor chip mounting portion of the heat dissipating substrate; and the hybrid integrated circuit board is mounted on the heat dissipating substrate by aligning the opening with the semiconductor chip. Hybrid integrated circuit device. （２）−放熱性基板の半導体チップ取付部分を凸状に形
成したことを特徴とする実用新案登録請求の範囲第１項
記載の混成集積回路装置。(2) - The hybrid integrated circuit device according to claim 1, wherein the semiconductor chip mounting portion of the heat dissipating substrate is formed in a convex shape.
JP1981101013U 1981-07-06 1981-07-06 Hybrid integrated circuit device Pending JPS587337U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981101013U JPS587337U (en) 1981-07-06 1981-07-06 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981101013U JPS587337U (en) 1981-07-06 1981-07-06 Hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPS587337U true JPS587337U (en) 1983-01-18

Family

ID=29895686

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981101013U Pending JPS587337U (en) 1981-07-06 1981-07-06 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS587337U (en)

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