JPS6252946U - - Google Patents
Info
- Publication number
- JPS6252946U JPS6252946U JP14493785U JP14493785U JPS6252946U JP S6252946 U JPS6252946 U JP S6252946U JP 14493785 U JP14493785 U JP 14493785U JP 14493785 U JP14493785 U JP 14493785U JP S6252946 U JPS6252946 U JP S6252946U
- Authority
- JP
- Japan
- Prior art keywords
- tab
- integrated circuit
- type leads
- outside
- circuit chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 description 2
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第1図aは本考案の一実施例の平面図、同図b
は同図aのA―A断面図、第2図a〜cは、第1
図の集積回路チツプの封入工程を説明するための
工程順の断面図、第3図a,bはそれぞれ従来の
タブ型リードを有する集積回路チツプの実装方法
の一例および他の一例を説明するための断面図で
ある。
1……セラミツクケース基体、2……タブ型リ
ードをもつ集積回路チツプ、3……タブ型リード
、4……セラミツク蓋板、5……配線基板、6…
…ケース本体、7……リードピン、8……蓋。
Figure 1a is a plan view of an embodiment of the present invention, Figure 1b is a plan view of an embodiment of the present invention.
is a sectional view taken along line A-A in Figure a, and Figures 2 a to c are sectional views of the first
Figures 3a and 3b are cross-sectional views of the process order for explaining the process of encapsulating an integrated circuit chip in the figure, and Figures 3a and 3b are for explaining an example and another example of a mounting method for an integrated circuit chip having conventional tab-type leads, respectively. FIG. DESCRIPTION OF SYMBOLS 1... Ceramic case base, 2... Integrated circuit chip with tab-shaped leads, 3... Tab-shaped leads, 4... Ceramic cover plate, 5... Wiring board, 6...
...Case body, 7... Lead pin, 8... Lid.
Claims (1)
プを、そのタブ型リードの外端側を外部に出した
状態で絶縁ケースに収容し、前記ケース外部に出
ているタブ型リードを外部リード端子としたこと
を特徴とする集積回路装置。 An integrated circuit chip having tab (TAB) type leads is housed in an insulating case with the outer ends of the tab type leads exposed to the outside, and the tab type leads exposed to the outside of the case are used as external lead terminals. An integrated circuit device characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14493785U JPS6252946U (en) | 1985-09-20 | 1985-09-20 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14493785U JPS6252946U (en) | 1985-09-20 | 1985-09-20 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6252946U true JPS6252946U (en) | 1987-04-02 |
Family
ID=31056009
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14493785U Pending JPS6252946U (en) | 1985-09-20 | 1985-09-20 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6252946U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0236556A (en) * | 1988-07-26 | 1990-02-06 | Matsushita Electric Works Ltd | Pin grid array and mounting of semiconductor element |
-
1985
- 1985-09-20 JP JP14493785U patent/JPS6252946U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0236556A (en) * | 1988-07-26 | 1990-02-06 | Matsushita Electric Works Ltd | Pin grid array and mounting of semiconductor element |
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