JPS61151348U - - Google Patents
Info
- Publication number
- JPS61151348U JPS61151348U JP3334785U JP3334785U JPS61151348U JP S61151348 U JPS61151348 U JP S61151348U JP 3334785 U JP3334785 U JP 3334785U JP 3334785 U JP3334785 U JP 3334785U JP S61151348 U JPS61151348 U JP S61151348U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- semiconductor package
- lead terminals
- view
- printed circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
Landscapes
- Electric Clocks (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図ないし第３図はこの考案の第１実施例を
示し、第１図は回路基板の平面図、第２図はその
断面図、第３図はその製造工程を示す図、第４図
ないし第６図は第２実施例を示し、第４図はその
側面図、第５図はその断面図、第６図は下側から
見た斜視図、第７図は第３実施例の断面図、第８
図および第９図は第４実施例を示し、第８図は回
路基板の平面図、第９図はその断面図である。
１，１１，３０……回路基板、２……半導体パ
ツケージ、３……プリント基板、４……半導体チ
ツプ、５……リードフレーム、５ａ，５ｂ……リ
ード端子、７……モールド樹脂、８……電子部品
、１０……電極端子、１２……フレキシブル基板
。
Figures 1 to 3 show the first embodiment of this invention, with Figure 1 being a plan view of the circuit board, Figure 2 being a sectional view thereof, Figure 3 being a diagram showing the manufacturing process, and Figure 4 being a diagram showing the manufacturing process. 6 to 6 show the second embodiment, FIG. 4 is a side view thereof, FIG. 5 is a sectional view thereof, FIG. 6 is a perspective view seen from below, and FIG. 7 is a sectional view of the third embodiment. Figure, 8th
9 and 9 show a fourth embodiment, FIG. 8 is a plan view of the circuit board, and FIG. 9 is a sectional view thereof. 1, 11, 30...Circuit board, 2...Semiconductor package, 3...Printed circuit board, 4...Semiconductor chip, 5...Lead frame, 5a, 5b...Lead terminal, 7...Mold resin, 8... ...Electronic component, 10... Electrode terminal, 12... Flexible board.
Claims (1)
封止してなる半導体パツケージと、この半導体パ
ツケージの前記リード端子に電気的接続される電
極端子が絶縁基板上に形成されたプリント基板と
からなる回路基板構造。 A circuit board consisting of a semiconductor package in which a semiconductor chip connected to lead terminals is sealed with resin, and a printed circuit board in which electrode terminals electrically connected to the lead terminals of the semiconductor package are formed on an insulating substrate. structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3334785U JPS61151348U (en) | 1985-03-11 | 1985-03-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3334785U JPS61151348U (en) | 1985-03-11 | 1985-03-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61151348U true JPS61151348U (en) | 1986-09-18 |
Family
ID=30535713
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3334785U Pending JPS61151348U (en) | 1985-03-11 | 1985-03-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61151348U (en) |
-
1985
- 1985-03-11 JP JP3334785U patent/JPS61151348U/ja active Pending