JPH0317625U - - Google Patents

Info

Publication number
JPH0317625U
JPH0317625U JP7706489U JP7706489U JPH0317625U JP H0317625 U JPH0317625 U JP H0317625U JP 7706489 U JP7706489 U JP 7706489U JP 7706489 U JP7706489 U JP 7706489U JP H0317625 U JPH0317625 U JP H0317625U
Authority
JP
Japan
Prior art keywords
chip
package
electrodes
electronic circuit
housed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7706489U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7706489U priority Critical patent/JPH0317625U/ja
Publication of JPH0317625U publication Critical patent/JPH0317625U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Die Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例の断面図、第２図は
本考案の一実施例の要部の平面図、破断面図、底
面図、第３図は従来の一例の断面図、第４図はリ
ードレスチツプキヤリアパツケージの一例の斜視
図である。 １…パツケージ、１ａ〜１ｄ…セラミツク板、
２…チツプ、４…接着剤、５…電極端子、６…ワ
イヤ。 Fig. 1 is a sectional view of an embodiment of the present invention, Fig. 2 is a plan view, a broken section view, and a bottom view of essential parts of an embodiment of the invention, and Fig. 3 is a sectional view of a conventional example. FIG. 4 is a perspective view of an example of a leadless chip carrier package. 1...Package, 1a to 1d...Ceramic board,
2... Chip, 4... Adhesive, 5... Electrode terminal, 6... Wire.

Claims (1)

【実用新案登録請求の範囲】 周囲に密着して外部装置との電気的接続を行な
う電極が形成されたパツケージ内に電子回路が形
成されたチツプを収納し、前記電極を介して前記
チツプと前記外部装置とを電気的に接続すると共
に前記チツプと前記パツケージとを電気的に結合
させた電子装置において、 前記チツプと前記パツケージとを導電性を有す
る接着剤により接着してなる電子装置。[Claims for Utility Model Registration] A chip on which an electronic circuit is formed is housed in a package in which electrodes are formed in close contact with the periphery for electrical connection with external devices, and the chip and the electronic circuit are connected via the electrodes. An electronic device electrically connected to an external device and electrically coupled to the chip and the package, wherein the chip and the package are bonded together using a conductive adhesive.
JP7706489U 1989-06-30 1989-06-30 Pending JPH0317625U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7706489U JPH0317625U (en) 1989-06-30 1989-06-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7706489U JPH0317625U (en) 1989-06-30 1989-06-30

Publications (1)

Publication Number Publication Date
JPH0317625U true JPH0317625U (en) 1991-02-21

Family

ID=31619099

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7706489U Pending JPH0317625U (en) 1989-06-30 1989-06-30

Country Status (1)

Country Link
JP (1) JPH0317625U (en)

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