JPS62160546U - - Google Patents
Info
- Publication number
- JPS62160546U JPS62160546U JP4804186U JP4804186U JPS62160546U JP S62160546 U JPS62160546 U JP S62160546U JP 4804186 U JP4804186 U JP 4804186U JP 4804186 U JP4804186 U JP 4804186U JP S62160546 U JPS62160546 U JP S62160546U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor element
- chip carrier
- circuit component
- fixed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
Description
第１図は、本考案の一実施例の斜視図、第２図
および第３図は本考案の一実施例の断面図、第４
図は従来装置の斜視図および等価回路図である。
〈符号の説明〉、１……基板、２……半導体素
子、３……チツプキヤリア、４……ワイヤ、５…
…サブストレート、６……電極、７……電極、８
……印刷抵抗、９……ハンダ。
FIG. 1 is a perspective view of an embodiment of the present invention, FIGS. 2 and 3 are sectional views of an embodiment of the present invention, and FIG. 4 is a perspective view of an embodiment of the present invention.
The figures are a perspective view and an equivalent circuit diagram of a conventional device. <Explanation of symbols> 1...Substrate, 2...Semiconductor element, 3...Chip carrier, 4...Wire, 5...
...substrate, 6...electrode, 7...electrode, 8
...Printed resistance, 9...Solder.
Claims (1)
体素子を固着し、上記サブストレートを基板に固
着し、上記サブストレートに設けた電極を介して
上記半導体素子と上記基板の電極とを接続するい
わゆるチツプキヤリア構造において、上記サブス
トレートの裏面と上記基板の表面との間に回路部
品を配設し、上記サブストレートの裏面に設けた
電極に上記回路部品を電気的に接続したことを特
徴とするチツプキヤリア構造。 In a so-called chip carrier structure in which a semiconductor element is fixed to the surface of a substrate made of an insulating material, the substrate is fixed to a substrate, and the semiconductor element and the electrode of the substrate are connected via an electrode provided on the substrate. A chip carrier structure characterized in that a circuit component is disposed between the back surface of the substrate and the front surface of the substrate, and the circuit component is electrically connected to an electrode provided on the back surface of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4804186U JPS62160546U (en) | 1986-04-02 | 1986-04-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4804186U JPS62160546U (en) | 1986-04-02 | 1986-04-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62160546U true JPS62160546U (en) | 1987-10-13 |
Family
ID=30869205
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4804186U Pending JPS62160546U (en) | 1986-04-02 | 1986-04-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62160546U (en) |
-
1986
- 1986-04-02 JP JP4804186U patent/JPS62160546U/ja active Pending