JPS6367253U - - Google Patents
Info
- Publication number
- JPS6367253U JPS6367253U JP1986161992U JP16199286U JPS6367253U JP S6367253 U JPS6367253 U JP S6367253U JP 1986161992 U JP1986161992 U JP 1986161992U JP 16199286 U JP16199286 U JP 16199286U JP S6367253 U JPS6367253 U JP S6367253U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- lead pattern
- semiconductor substrate
- semiconductor device
- central recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 4
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第1図aはこの考案の一実施例であるピングリ
ツドアレイ半導体パツケージに収納された半導体
装置の側面断面図、第1図bは、第1図aの半導
体装置の一部切断正面図、第2図aは、従来のピ
ングリツドアレイ半導体パツケージに収納された
半導体装置の側面断面図、第2図bは、第2図a
の半導体装置の一部切断正面図。
1……半導体基板、2c……凹部、3……半導
体素子、4……電極端子、5……ワイヤ、6……
リードパターン、7……スルーホール、8……外
部端子。
FIG. 1a is a side sectional view of a semiconductor device housed in a pin grid array semiconductor package which is an embodiment of this invention, FIG. 1b is a partially cutaway front view of the semiconductor device of FIG. 1a, FIG. 2a is a side sectional view of a semiconductor device housed in a conventional pin grid array semiconductor package, and FIG. 2b is a side sectional view of a semiconductor device housed in a conventional pin grid array semiconductor package.
FIG. 2 is a partially cutaway front view of the semiconductor device. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2c... Recessed part, 3... Semiconductor element, 4... Electrode terminal, 5... Wire, 6...
Lead pattern, 7...Through hole, 8...External terminal.
Claims (1)
板内の全面にわたり、絶縁状態でリードパターン
を埋設し、かつ、このリードパターンに通ずる外
部端子を半導体基板の底面より外部に突設したこ
とを特徴とする半導体装置。 (2) リードパターンは、半導体基板の中央凹部
に露出配設し、かつ絶縁層を介して、半導体素子
を設けたことを特徴とする実用新案登録請求の範
囲第(1)項記載の半導体装置。[Scope of Claim for Utility Model Registration] (1) A lead pattern is buried in an insulating state over the entire surface of a semiconductor substrate in which a semiconductor element is arranged in a central recess, and an external terminal connected to this lead pattern is connected to the bottom surface of the semiconductor substrate. A semiconductor device characterized by protruding outward. (2) The semiconductor device according to claim 1, wherein the lead pattern is exposed in the central recess of the semiconductor substrate, and the semiconductor element is provided with an insulating layer interposed therebetween. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986161992U JPS6367253U (en) | 1986-10-22 | 1986-10-22 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986161992U JPS6367253U (en) | 1986-10-22 | 1986-10-22 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6367253U true JPS6367253U (en) | 1988-05-06 |
Family
ID=31088830
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1986161992U Pending JPS6367253U (en) | 1986-10-22 | 1986-10-22 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6367253U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07202062A (en) * | 1993-12-28 | 1995-08-04 | Nec Corp | Semiconductor device |
-
1986
- 1986-10-22 JP JP1986161992U patent/JPS6367253U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07202062A (en) * | 1993-12-28 | 1995-08-04 | Nec Corp | Semiconductor device |