JPS61201348U - - Google Patents
Info
- Publication number
- JPS61201348U JPS61201348U JP8539585U JP8539585U JPS61201348U JP S61201348 U JPS61201348 U JP S61201348U JP 8539585 U JP8539585 U JP 8539585U JP 8539585 U JP8539585 U JP 8539585U JP S61201348 U JPS61201348 U JP S61201348U
- Authority
- JP
- Japan
- Prior art keywords
- insulating resin
- substrate
- semiconductor device
- electrically insulating
- sealed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims description 5
- 229920005989 resin Polymers 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 2
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図は本考案の一実施例の概略断面図、第２
図は従来例の概略断面図である。
１……基板、２……素子、４……電気絶縁性樹
脂、６……被覆層、７……絶縁性樹脂被膜。
Fig. 1 is a schematic sectional view of one embodiment of the present invention;
The figure is a schematic sectional view of a conventional example. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Element, 4... Electrical insulating resin, 6... Covering layer, 7... Insulating resin coating.
Claims (1)
樹脂にて封止した半導体装置において、 上記基板の下面と電気絶縁性樹脂との間に絶縁
樹脂被膜を形成したことを特徴とする半導体装置
。[Scope of claim for utility model registration] In a semiconductor device in which an element is mounted on the top surface of a substrate and the whole is sealed with electrically insulating resin, an insulating resin coating is formed between the bottom surface of the substrate and the electrically insulating resin. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8539585U JPS61201348U (en) | 1985-06-06 | 1985-06-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8539585U JPS61201348U (en) | 1985-06-06 | 1985-06-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61201348U true JPS61201348U (en) | 1986-12-17 |
Family
ID=30635753
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8539585U Pending JPS61201348U (en) | 1985-06-06 | 1985-06-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61201348U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6027440B2 (en) * | 1976-06-25 | 1985-06-28 | 株式会社東芝 | automatic deposit machine |
| JPS6027441B2 (en) * | 1977-01-21 | 1985-06-28 | 日本電気株式会社 | amplitude equalizer |
-
1985
- 1985-06-06 JP JP8539585U patent/JPS61201348U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6027440B2 (en) * | 1976-06-25 | 1985-06-28 | 株式会社東芝 | automatic deposit machine |
| JPS6027441B2 (en) * | 1977-01-21 | 1985-06-28 | 日本電気株式会社 | amplitude equalizer |