JPH0410349U - - Google Patents
Info
- Publication number
- JPH0410349U JPH0410349U JP1990050848U JP5084890U JPH0410349U JP H0410349 U JPH0410349 U JP H0410349U JP 1990050848 U JP1990050848 U JP 1990050848U JP 5084890 U JP5084890 U JP 5084890U JP H0410349 U JPH0410349 U JP H0410349U
- Authority
- JP
- Japan
- Prior art keywords
- internal lead
- lead connection
- chip mounting
- ceramic substrate
- diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 4
- 239000002131 composite material Substances 0.000 claims description 3
- 238000005219 brazing Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Description
第１図ａ，ｂおよびｃはそれぞれ本考案の一実
施例を示す複合ダイオード回路素子の透視平面図
、Ａ−Ａ′断面図およびチツプの接続等価回路図
、第２図ａ，ｂ〜第４図ａ，ｂはそれぞれ上記実
施例におけるダイオードチツプ間の異なる接続関
係を示す透視平面図およびチツプの接続等価回路
、第５図ａ，ｂおよびｃはそれぞれ本考案の他の
実施例を示す複合ダイオード回路素子の透視平面
図、Ｂ−Ｂ′断面図およびチツプの接続等価回路
図、第６図ａ，ｂ〜第８図ａ，ｂは上記実施例に
おけるダイオードチツプ間の異なる接続関係を示
す透視平面図およびチツプの接続等価回路図、第
９図ａ，ｂはそれぞれ従来のダイオード回路素子
の透視平面図およびそのＣ−Ｃ′断面図である。
１ａ，１ｂ……ダイオードチツプ、２……セラ
ミツク基板部材、３……セラミツク壁部材、４…
…セラミツク蓋部材、５ａ，５ｂ……チツプ取付
面、６ａ〜６ｆ，６ｃ′，６ｆ′……内部リード
接続面、７……ボンデイングワイヤ、８……ろう
材、９ａ，９ｂ……外部リード端子、１０……壁
部材側面上の導通面。
Figures 1a, b and c are a perspective plan view, an A-A' sectional view and a chip connection equivalent circuit diagram, respectively, of a composite diode circuit element showing an embodiment of the present invention, and Figures 2a, b to 4 Figures a and b are perspective plan views and chip connection equivalent circuits showing different connection relationships between diode chips in the above embodiment, respectively, and Figures a, b and c are composite diodes showing other embodiments of the present invention, respectively. A perspective plan view of the circuit element, a BB' sectional view, and an equivalent circuit diagram of the chip connections, FIGS. 6a, b to 8a, b are perspective planes showing different connection relationships between the diode chips in the above embodiment 9A and 9B are a perspective plan view and a sectional view taken along the line C-C' of a conventional diode circuit element, respectively. 1a, 1b...Diode chip, 2...Ceramic substrate member, 3...Ceramic wall member, 4...
... Ceramic lid member, 5a, 5b... Chip mounting surface, 6a to 6f, 6c', 6f'... Internal lead connection surface, 7... Bonding wire, 8... Brazing metal, 9a, 9b... External lead terminal , 10... Conductive surface on the side surface of the wall member.
Claims (1)
のセラミツク基板部材と、ろう材を介し外部リー
ド端子とそれぞれ電気接続される一対の内部リー
ド接続面および壁部材側面に形成する導通面を介
し前記下段セラミツク基板部材上のチツプ取付面
とそれぞれ電気接続される複数個の内部リード接
続面をそれぞれ部材上部面上に形成する中段のセ
ラミツク壁部材と、上段のセラミツク蓋部材とか
らなるセラミツク封止容器と、前記下段のセラミ
ツク基板部材上のチツプ取付面にカソード電極を
載置し固着される複数個のダイオードチツプと、
該ダイオードのアノード電極と前記内部リード接
続面または複数個の内部リード接続面間をそれぞ
れ選択的に電気接続する金属導体線とを備えるこ
とを特徴とする複合ダイオード回路素子。 A lower ceramic substrate member having a plurality of chip mounting surfaces on its inner surface, a pair of internal lead connection surfaces electrically connected to external lead terminals via a brazing material, and a conductive surface formed on the side surface of the wall member. A ceramic sealed container consisting of a middle ceramic wall member having a plurality of internal lead connection surfaces each formed on the upper surface of the member, each electrically connected to a chip mounting surface on a lower ceramic substrate member, and an upper ceramic lid member. and a plurality of diode chips with cathode electrodes placed and fixed on the chip mounting surface of the lower ceramic substrate member;
A composite diode circuit element comprising metal conductor wires selectively electrically connecting the anode electrode of the diode and the internal lead connection surface or between a plurality of internal lead connection surfaces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990050848U JPH0410349U (en) | 1990-05-16 | 1990-05-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990050848U JPH0410349U (en) | 1990-05-16 | 1990-05-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0410349U true JPH0410349U (en) | 1992-01-29 |
Family
ID=31569754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990050848U Pending JPH0410349U (en) | 1990-05-16 | 1990-05-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0410349U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5424143A (en) * | 1977-07-25 | 1979-02-23 | Oki Masaharu | Cash register toy |
-
1990
- 1990-05-16 JP JP1990050848U patent/JPH0410349U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5424143A (en) * | 1977-07-25 | 1979-02-23 | Oki Masaharu | Cash register toy |
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