JPS62163952U - - Google Patents

Info

Publication number
JPS62163952U
JPS62163952U JP5173186U JP5173186U JPS62163952U JP S62163952 U JPS62163952 U JP S62163952U JP 5173186 U JP5173186 U JP 5173186U JP 5173186 U JP5173186 U JP 5173186U JP S62163952 U JPS62163952 U JP S62163952U
Authority
JP
Japan
Prior art keywords
chip
insulating layer
fixed
metal base
circuit element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5173186U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5173186U priority Critical patent/JPS62163952U/ja
Publication of JPS62163952U publication Critical patent/JPS62163952U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第3図は本考案にかかる回路装置の
実施例で、第1図は第1実施例を示す一部切截の
斜視図、第2図は第2実施例を示す斜視図、第3
図は第3実施例を示す斜視図、第4図は従来の回
路装置を示す一部切截の斜視図である。 1,21…金属ベース、4,28…弾性表面波
素子、7,32,37,38,39…金属性キヤ
ツプ、8,23…リード端子、13,35…IC
素子。
1 to 3 show embodiments of the circuit device according to the present invention, FIG. 1 is a partially cutaway perspective view showing the first embodiment, FIG. 2 is a perspective view showing the second embodiment, Third
This figure is a perspective view showing a third embodiment, and FIG. 4 is a partially cutaway perspective view showing a conventional circuit device. 1, 21... Metal base, 4, 28... Surface acoustic wave element, 7, 32, 37, 38, 39... Metal cap, 8, 23... Lead terminal, 13, 35... IC
element.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] リード端子を植設した金属ベース上に、絶縁層
を形成し、前記絶縁層上に回路配線を設けるとと
もにチツプ状の回路素子を固着し、前記チツプ状
の回路素子を封止する金属性キヤツプを前記金属
ベースに固定してなる構成の回路装置。
An insulating layer is formed on a metal base on which lead terminals are implanted, circuit wiring is provided on the insulating layer, a chip-shaped circuit element is fixed, and a metal cap is provided to seal the chip-shaped circuit element. A circuit device configured to be fixed to the metal base.
JP5173186U 1986-04-07 1986-04-07 Pending JPS62163952U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5173186U JPS62163952U (en) 1986-04-07 1986-04-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5173186U JPS62163952U (en) 1986-04-07 1986-04-07

Publications (1)

Publication Number Publication Date
JPS62163952U true JPS62163952U (en) 1987-10-17

Family

ID=30876261

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5173186U Pending JPS62163952U (en) 1986-04-07 1986-04-07

Country Status (1)

Country Link
JP (1) JPS62163952U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61280639A (en) * 1985-06-05 1986-12-11 Nec Yamagata Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61280639A (en) * 1985-06-05 1986-12-11 Nec Yamagata Ltd Semiconductor device

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