JPS6268231U - - Google Patents
Info
- Publication number
- JPS6268231U JPS6268231U JP1985159407U JP15940785U JPS6268231U JP S6268231 U JPS6268231 U JP S6268231U JP 1985159407 U JP1985159407 U JP 1985159407U JP 15940785 U JP15940785 U JP 15940785U JP S6268231 U JPS6268231 U JP S6268231U
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon
- opening
- semiconductor device
- check terminal
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
Description
第１図ａ，ｂは本考案の一実施例を示す平面図
、断面図、第２図ａ，ｂは従来構造図である。
１，５……金属、２，７……絶縁酸化膜、３，
６……開口、４……ポリシリコン。
FIGS. 1A and 1B are a plan view and a sectional view showing an embodiment of the present invention, and FIGS. 2A and 2B are conventional structural views. 1,5...Metal, 2,7...Insulating oxide film, 3,
6...Opening, 4...Polysilicon.
Claims (1)
記チエツク端子はポリシリコンで構成され、さら
に、前記ポリシリコンと外部金属を接続する為の
第１の開口と前記集積回路の内部金属と前記ポリ
シリコンと接続する為の第２の開口を有すること
を特徴とする半導体装置。 In a semiconductor device having a check terminal, the check terminal is made of polysilicon, and further includes a first opening for connecting the polysilicon to an external metal, and a first opening for connecting the internal metal of the integrated circuit to the polysilicon. A semiconductor device characterized by having a second opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985159407U JPS6268231U (en) | 1985-10-17 | 1985-10-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985159407U JPS6268231U (en) | 1985-10-17 | 1985-10-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6268231U true JPS6268231U (en) | 1987-04-28 |
Family
ID=31083806
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985159407U Pending JPS6268231U (en) | 1985-10-17 | 1985-10-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6268231U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5758790A (en) * | 1980-09-26 | 1982-04-08 | Yoshikazu Hamamoto | Compound shutter for building |
| JPS5789239A (en) * | 1980-11-26 | 1982-06-03 | Seiko Epson Corp | Semiconductor integrated circuit |
-
1985
- 1985-10-17 JP JP1985159407U patent/JPS6268231U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5758790A (en) * | 1980-09-26 | 1982-04-08 | Yoshikazu Hamamoto | Compound shutter for building |
| JPS5789239A (en) * | 1980-11-26 | 1982-06-03 | Seiko Epson Corp | Semiconductor integrated circuit |