JPS6258048U - - Google Patents

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Publication number
JPS6258048U
JPS6258048U JP14927685U JP14927685U JPS6258048U JP S6258048 U JPS6258048 U JP S6258048U JP 14927685 U JP14927685 U JP 14927685U JP 14927685 U JP14927685 U JP 14927685U JP S6258048 U JPS6258048 U JP S6258048U
Authority
JP
Japan
Prior art keywords
semiconductor package
terminals
utility
scope
registration request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14927685U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14927685U priority Critical patent/JPS6258048U/ja
Publication of JPS6258048U publication Critical patent/JPS6258048U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第3図は本考案に係る半導体パツ
ケージの端子構成の実施例を示し、第1図は第1
実施例を示す斜視図、第2図aは第1図に示す実
施例における第1段目の製造工程の説明図、第2
図bは第1図に示す実施例における第2段目の製
造工程の説明図、第2図cは第1図に示す実施例
における第3段目の製造工程の説明図、第3図は
第2実施例を示す斜視図である。 1c,6a……上側端子、1d,6b……下側
端子、4,5……半導体パツケージ。
1 to 3 show an embodiment of the terminal structure of a semiconductor package according to the present invention, and FIG.
FIG. 2a is an explanatory diagram of the manufacturing process of the first stage in the embodiment shown in FIG.
Figure b is an explanatory diagram of the second stage manufacturing process in the embodiment shown in Figure 1, Figure 2 c is an explanatory diagram of the third stage manufacturing process in the embodiment shown in Figure 1, and Figure 3 is an explanatory diagram of the third stage manufacturing process in the embodiment shown in Figure 1. FIG. 3 is a perspective view showing a second embodiment. 1c, 6a... upper terminal, 1d, 6b... lower terminal, 4, 5... semiconductor package.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体パツケージにおいて、該半導体パツケー
ジの相対する両面に端子を突設形成したことを特
徴とする半導体パツケージの端子構成。
1. A terminal configuration for a semiconductor package, characterized in that terminals are formed protrudingly on opposing surfaces of the semiconductor package.
JP14927685U 1985-09-30 1985-09-30 Pending JPS6258048U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14927685U JPS6258048U (en) 1985-09-30 1985-09-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14927685U JPS6258048U (en) 1985-09-30 1985-09-30

Publications (1)

Publication Number Publication Date
JPS6258048U true JPS6258048U (en) 1987-04-10

Family

ID=31064330

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14927685U Pending JPS6258048U (en) 1985-09-30 1985-09-30

Country Status (1)

Country Link
JP (1) JPS6258048U (en)

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