JPH0353854U - - Google Patents
Info
- Publication number
- JPH0353854U JPH0353854U JP11537189U JP11537189U JPH0353854U JP H0353854 U JPH0353854 U JP H0353854U JP 11537189 U JP11537189 U JP 11537189U JP 11537189 U JP11537189 U JP 11537189U JP H0353854 U JPH0353854 U JP H0353854U
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- semiconductor element
- lead frame
- chip component
- discrete chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Description
第１図は本考案に係る半導体装置の実施例を示
す構成図、第２図は従来例を示す構成図である。
２１……Ｓｉ基板、２３……絶縁層、２４，２
５……ベアチツプＩＣ、２７……デイスクリート
チツプ部品、３０，３１，３２，３３……配線パ
ターン、４０，４１……インナーリードフレーム
、４３，４４……ボンデイングワイヤ。
FIG. 1 is a block diagram showing an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a block diagram showing a conventional example. 21...Si substrate, 23...Insulating layer, 24,2
5... Bear chip IC, 27... Discrete chip component, 30, 31, 32, 33... Wiring pattern, 40, 41... Inner lead frame, 43, 44... Bonding wire.
Claims (1)
と、 該第１の半導体素子に形成される絶縁層と、 該絶縁層上に配設され、リードフレームに接続
される第２の半導体素子および／またはデイスク
リートチツプ部品と、 前記絶縁層に形成されるとともに、前記第２の
半導体素子および／またはデイスクリートチツプ
部品とを接続する配線パターンと、 を備えて構成されることを特徴とする半導体装置
。[Claims for Utility Model Registration] A first semiconductor element disposed on a lead frame, an insulating layer formed on the first semiconductor element, and an insulating layer disposed on the insulating layer and connected to the lead frame. a second semiconductor element and/or discrete chip component; and a wiring pattern formed on the insulating layer and connecting the second semiconductor element and/or discrete chip component. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11537189U JPH0353854U (en) | 1989-09-29 | 1989-09-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11537189U JPH0353854U (en) | 1989-09-29 | 1989-09-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0353854U true JPH0353854U (en) | 1991-05-24 |
Family
ID=31663702
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11537189U Pending JPH0353854U (en) | 1989-09-29 | 1989-09-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0353854U (en) |
-
1989
- 1989-09-29 JP JP11537189U patent/JPH0353854U/ja active Pending