JPS63170983U - - Google Patents

Info

Publication number
JPS63170983U
JPS63170983U JP6321587U JP6321587U JPS63170983U JP S63170983 U JPS63170983 U JP S63170983U JP 6321587 U JP6321587 U JP 6321587U JP 6321587 U JP6321587 U JP 6321587U JP S63170983 U JPS63170983 U JP S63170983U
Authority
JP
Japan
Prior art keywords
semiconductor element
ceramic substrate
coating
alumina ceramic
view
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6321587U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6321587U priority Critical patent/JPS63170983U/ja
Publication of JPS63170983U publication Critical patent/JPS63170983U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例のワイヤボンデイグ
完了後の平面図、第2図は本考案の他の実施例の
平面図、第3図は従来例のワイヤボンデイグ完了
後の平面図、第4図は従来例構造の製品の断面図
、第5図は従来例構造で、コーテイング樹脂塗布
範囲が不足している製品の断面図、第6図は従来
例構造で、コーテイグ樹脂塗布範囲が過多な製品
の断面図である。 1……アルミナセラミツク基板、2……導電体
パターン、3……半導体素子、4……金線あるい
はアルミ線、5……コーテイング樹脂、6……外
装樹脂、7……外部引き出しリード線、8……半
田、9……目印用導電体パターン。
Fig. 1 is a plan view of one embodiment of the present invention after wire bonding is completed, Fig. 2 is a plan view of another embodiment of the present invention, Fig. 3 is a plan view of a conventional example after completion of wire bonding, and Fig. 4 is a cross-sectional view of a product with a conventional structure, Figure 5 is a cross-sectional view of a product with a conventional structure and an insufficient coating area of the coating resin, and Figure 6 is a cross-sectional view of a product with a conventional structure and an excessive coating area of the coating resin. FIG. DESCRIPTION OF SYMBOLS 1... Alumina ceramic substrate, 2... Conductor pattern, 3... Semiconductor element, 4... Gold wire or aluminum wire, 5... Coating resin, 6... Exterior resin, 7... External lead wire, 8 ...Solder, 9...Conductor pattern for mark.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体素子を搭載したアルミナセラミツク基板
に於て、前記半導体素子をコーテイング封止する
樹脂の塗布範囲の境界を明確に示す独立したパタ
ーンを前記アルミナセラミツク基板上に有する事
を特徴とする混成集積回路装置。
A hybrid integrated circuit device, characterized in that an alumina ceramic substrate on which a semiconductor element is mounted has an independent pattern on the alumina ceramic substrate that clearly indicates the boundary of a coating range of a resin for coating and sealing the semiconductor element. .
JP6321587U 1987-04-24 1987-04-24 Pending JPS63170983U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6321587U JPS63170983U (en) 1987-04-24 1987-04-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6321587U JPS63170983U (en) 1987-04-24 1987-04-24

Publications (1)

Publication Number Publication Date
JPS63170983U true JPS63170983U (en) 1988-11-07

Family

ID=30898236

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6321587U Pending JPS63170983U (en) 1987-04-24 1987-04-24

Country Status (1)

Country Link
JP (1) JPS63170983U (en)

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