JPS61192447U - - Google Patents
Info
- Publication number
- JPS61192447U JPS61192447U JP7727085U JP7727085U JPS61192447U JP S61192447 U JPS61192447 U JP S61192447U JP 7727085 U JP7727085 U JP 7727085U JP 7727085 U JP7727085 U JP 7727085U JP S61192447 U JPS61192447 U JP S61192447U
- Authority
- JP
- Japan
- Prior art keywords
- inner lead
- upper inner
- semiconductor chip
- recess
- parts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000000919 ceramic Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Die Bonding (AREA)
Description
第１図Ａは本考案に係るセラミツクパツケージ
の平面図、同図Ｂはこの断面図、第２図は従来の
セラミツクパツケージの断面図である。
図において、１は多層セラミツク基板、２は半
導体チツプ、３，６は上段インナーリード部、４
は下段インナーリード部、５はワイヤ、７は凹部
、８はインナーリード、９は絶縁性突出部である
。
FIG. 1A is a plan view of a ceramic package according to the present invention, FIG. 1B is a sectional view thereof, and FIG. 2 is a sectional view of a conventional ceramic package. In the figure, 1 is a multilayer ceramic substrate, 2 is a semiconductor chip, 3 and 6 are upper inner lead parts, and 4 is a semiconductor chip.
5 is a lower inner lead portion, 5 is a wire, 7 is a recessed portion, 8 is an inner lead, and 9 is an insulating protrusion.
Claims (1)
体チツプ２を収容する凹部７と、該凹部の周辺部
に配設された下段インナーリード４と、該下段イ
ンナーリード部４の外側に配設された上段インナ
ーリード部６と、該下段及び上段インナーリード
部との間に設けられた絶縁性突出部９とを備え、
前記下段及び上段インナーリード部４，６がそれ
ぞれワイヤ５により前記半導体チツプ２に接続さ
れてなることを特徴とする半導体装置。 A recess 7 provided on the surface of the multilayer ceramic substrate 1 and accommodating the semiconductor chip 2, a lower inner lead 4 disposed around the recess, and an upper inner lead 4 disposed outside the lower inner lead 4. Comprising an inner lead part 6 and an insulating protrusion part 9 provided between the lower and upper inner lead parts,
A semiconductor device characterized in that the lower and upper inner lead parts 4 and 6 are connected to the semiconductor chip 2 by wires 5, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7727085U JPS61192447U (en) | 1985-05-24 | 1985-05-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7727085U JPS61192447U (en) | 1985-05-24 | 1985-05-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61192447U true JPS61192447U (en) | 1986-11-29 |
Family
ID=30620184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7727085U Pending JPS61192447U (en) | 1985-05-24 | 1985-05-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61192447U (en) |
-
1985
- 1985-05-24 JP JP7727085U patent/JPS61192447U/ja active Pending