JPH01165657U - - Google Patents
Info
- Publication number
- JPH01165657U JPH01165657U JP6310288U JP6310288U JPH01165657U JP H01165657 U JPH01165657 U JP H01165657U JP 6310288 U JP6310288 U JP 6310288U JP 6310288 U JP6310288 U JP 6310288U JP H01165657 U JPH01165657 U JP H01165657U
- Authority
- JP
- Japan
- Prior art keywords
- main body
- body portion
- semiconductor chip
- lead terminals
- exposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Description
第１図は本考案の第１の実施例の斜視図、第２
図は第１図の第１の実施例の断面図、第３図は本
考案の第２の実施例の斜視図、第４図は第３図の
第２の実施例の断面図、第５図は従来のパツケー
ジの一例の斜視図である。
１，１ａ，１ｂ……本体部、２，２ａ……リー
ド端子、３……端子、４……露出面、５……ボン
デイングワイヤ、６……半導体チツプ、７……穴
。
Fig. 1 is a perspective view of the first embodiment of the present invention;
The figures are a sectional view of the first embodiment shown in FIG. 1, FIG. 3 is a perspective view of the second embodiment of the present invention, FIG. 4 is a sectional view of the second embodiment shown in FIG. The figure is a perspective view of an example of a conventional package. DESCRIPTION OF SYMBOLS 1, 1a, 1b... Main body part, 2, 2a... Lead terminal, 3... Terminal, 4... Exposed surface, 5... Bonding wire, 6... Semiconductor chip, 7... Hole.
Claims (1)
半導体チツプのそれぞれの電極に接続され前記本
体部から外部に導出される複数のリード端子と、
前記本体部に上面に設けられ前記リード端子それ
ぞれの一部が露出する複数の露出面とを有するこ
とを特徴とするパツケージ。 a main body portion housing a semiconductor chip therein; a plurality of lead terminals connected to respective electrodes of the semiconductor chip and led out from the main body portion;
A package characterized in that the main body portion has a plurality of exposed surfaces provided on the upper surface from which a portion of each of the lead terminals is exposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6310288U JPH01165657U (en) | 1988-05-12 | 1988-05-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6310288U JPH01165657U (en) | 1988-05-12 | 1988-05-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01165657U true JPH01165657U (en) | 1989-11-20 |
Family
ID=31288631
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6310288U Pending JPH01165657U (en) | 1988-05-12 | 1988-05-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01165657U (en) |
-
1988
- 1988-05-12 JP JP6310288U patent/JPH01165657U/ja active Pending