JPS62145346U - - Google Patents
Info
- Publication number
- JPS62145346U JPS62145346U JP3502386U JP3502386U JPS62145346U JP S62145346 U JPS62145346 U JP S62145346U JP 3502386 U JP3502386 U JP 3502386U JP 3502386 U JP3502386 U JP 3502386U JP S62145346 U JPS62145346 U JP S62145346U
- Authority
- JP
- Japan
- Prior art keywords
- bonded
- lead terminals
- semiconductor chips
- semiconductor
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Description
第１図は、この考案に係る半導体装置を示す斜
視図、第２図は、断面図、第３図は他の実施例を
示す断面図、第４図は、従来の半導体装置を示す
断面図である。
２：絶縁シート、３，３Ａ：集積回路本体、４
：樹脂モールド、３１，３１ａ：中央基板、３２
，３２ａ：リード端子、３３，３３ａ：半導体チ
ツプ、３４，３４ａ：Ａｕ線。
FIG. 1 is a perspective view showing a semiconductor device according to this invention, FIG. 2 is a sectional view, FIG. 3 is a sectional view showing another embodiment, and FIG. 4 is a sectional view showing a conventional semiconductor device. It is. 2: Insulating sheet, 3, 3A: Integrated circuit body, 4
: Resin mold, 31, 31a: Center board, 32
, 32a: lead terminal, 33, 33a: semiconductor chip, 34, 34a: Au wire.
Claims (1)
チツプをダイボンデイングし、この半導体チツプ
とリード端子とを金属線でワイヤボンデイングし
て成る複数の集積回路本体を、それぞれ絶縁シー
トを介して前記半導体チツプの表面が反対向きに
なる状態で接合させ樹脂モールドしたことを特徴
とする半導体装置。 Semiconductor chips are die-bonded to a central substrate with lead terminals arranged on both sides, and the semiconductor chips and lead terminals are wire-bonded using metal wires to form a plurality of integrated circuit bodies, each of which is connected to the semiconductor chip through an insulating sheet. A semiconductor device characterized by being bonded with their surfaces facing in opposite directions and molded with resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3502386U JPS62145346U (en) | 1986-03-10 | 1986-03-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3502386U JPS62145346U (en) | 1986-03-10 | 1986-03-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62145346U true JPS62145346U (en) | 1987-09-12 |
Family
ID=30844130
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3502386U Pending JPS62145346U (en) | 1986-03-10 | 1986-03-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62145346U (en) |
-
1986
- 1986-03-10 JP JP3502386U patent/JPS62145346U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS62145346U (en) | ||
| JPS646038U (en) | ||
| JPH0245676U (en) | ||
| JPS6375069U (en) | ||
| JPH01165657U (en) | ||
| JPS63187330U (en) | ||
| JPS61123544U (en) | ||
| JPS59112954U (en) | Insulator-encapsulated semiconductor device | |
| JPH0298649U (en) | ||
| JPS63128745U (en) | ||
| JPH03116032U (en) | ||
| JPS62126845U (en) | ||
| JPS64332U (en) | ||
| JPH02146437U (en) | ||
| JPS63113979U (en) | ||
| JPS6390861U (en) | ||
| JPH0474458U (en) | ||
| JPH01112044U (en) | ||
| JPH01125541U (en) | ||
| JPH0275736U (en) | ||
| JPS6181141U (en) | ||
| JPS6232556U (en) | ||
| JPS62134240U (en) | ||
| JPS62154644U (en) | ||
| JPH01175883U (en) |