JPH0298649U - - Google Patents
Info
- Publication number
- JPH0298649U JPH0298649U JP788289U JP788289U JPH0298649U JP H0298649 U JPH0298649 U JP H0298649U JP 788289 U JP788289 U JP 788289U JP 788289 U JP788289 U JP 788289U JP H0298649 U JPH0298649 U JP H0298649U
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor device
- semiconductor element
- package resin
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims description 5
- 229920005989 resin Polymers 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第1図は本考案の第1実施例の斜視図、第2図
はその一部破断平面図、第3図は本考案の第2実
施例の斜視図、第4図はその一部破断平面図、第
5図は従来の樹脂封止型半導体装置の斜視図、第
6図はその一部破断平面図である。
1……リード、2……素子搭載部、3……トラ
ンジスタチツプ、4,5……リード、4a,5a
……基部、6……ボンデイングワイヤ、7……パ
ツケージ樹脂、7a,7b,7c……側面、8…
…パツケージ樹脂、8a……底面、8b……周面
、9……パツケージ樹脂。
Fig. 1 is a perspective view of the first embodiment of the present invention, Fig. 2 is a partially cutaway plan view thereof, Fig. 3 is a perspective view of the second embodiment of the present invention, and Fig. 4 is a partially cutaway plan view thereof. 5 is a perspective view of a conventional resin-sealed semiconductor device, and FIG. 6 is a partially cutaway plan view thereof. 1...Lead, 2...Element mounting part, 3...Transistor chip, 4, 5...Lead, 4a, 5a
...Base, 6...Bonding wire, 7...Package resin, 7a, 7b, 7c...Side surface, 8...
...Package resin, 8a...Bottom surface, 8b...Surrounding surface, 9...Package resin.
Claims (1)
記半導体素子に電気接続された複数本のリードを
突出してなる半導体装置において、前記複数本の
リードをパツケージ樹脂の夫々異なる面から突出
させたことを特徴とする樹脂封止型半導体装置。 A semiconductor device comprising a plurality of leads electrically connected to the semiconductor element protruding from a package resin in which a semiconductor element is encapsulated, characterized in that the plurality of leads protrude from different surfaces of the package resin. Resin-sealed semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP788289U JPH0298649U (en) | 1989-01-26 | 1989-01-26 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP788289U JPH0298649U (en) | 1989-01-26 | 1989-01-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0298649U true JPH0298649U (en) | 1990-08-06 |
Family
ID=31213279
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP788289U Pending JPH0298649U (en) | 1989-01-26 | 1989-01-26 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0298649U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023136074A1 (en) * | 2022-01-13 | 2023-07-20 | ローム株式会社 | Semiconductor device |
-
1989
- 1989-01-26 JP JP788289U patent/JPH0298649U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023136074A1 (en) * | 2022-01-13 | 2023-07-20 | ローム株式会社 | Semiconductor device |