JPS63113979U - - Google Patents
Info
- Publication number
- JPS63113979U JPS63113979U JP349787U JP349787U JPS63113979U JP S63113979 U JPS63113979 U JP S63113979U JP 349787 U JP349787 U JP 349787U JP 349787 U JP349787 U JP 349787U JP S63113979 U JPS63113979 U JP S63113979U
- Authority
- JP
- Japan
- Prior art keywords
- metal pad
- chip
- substrate bias
- generation circuit
- bias generation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- 238000007789 sealing Methods 0.000 claims 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案のデユアルインラインパツケー
ジの実施例を示し、ａは外観斜視図、ｂは一部モ
ールドを除去した平面図である。
１……ＩＣチツプ、２……金属パツド、３……
ボンデイングパツド、４……リード端子、５……
ボンデイングワイヤ、６……プラスチツクモール
ド、７……くぼみ、８……導体片、９……基板バ
イアス測定端子。
FIG. 1 shows an embodiment of the dual in-line package of the present invention, in which a is an external perspective view and b is a plan view with a part of the mold removed. 1...IC chip, 2...metal pad, 3...
Bonding pad, 4... Lead terminal, 5...
Bonding wire, 6... plastic mold, 7... recess, 8... conductor piece, 9... substrate bias measurement terminal.
Claims (1)
封止するデユアルインライン形ＩＣパツケージに
おいて、前記ＩＣチツプをマウントし電気的に前
記基板バイアス発生回路の出力につながる金属パ
ツドの一部、あるいはこの金属パツドにつながる
導体片が、封止体の外部に露出していることを特
徴とするＩＣパツケージ。 In a dual-in-line IC package that encapsulates an IC chip with a built-in substrate bias generation circuit, a part of a metal pad on which the IC chip is mounted and electrically connected to the output of the substrate bias generation circuit, or a metal pad connected to this metal pad. An IC package characterized in that a conductor piece is exposed to the outside of a sealing body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP349787U JPS63113979U (en) | 1987-01-16 | 1987-01-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP349787U JPS63113979U (en) | 1987-01-16 | 1987-01-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63113979U true JPS63113979U (en) | 1988-07-22 |
Family
ID=30783306
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP349787U Pending JPS63113979U (en) | 1987-01-16 | 1987-01-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63113979U (en) |
-
1987
- 1987-01-16 JP JP349787U patent/JPS63113979U/ja active Pending
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