JPS5883150U - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS5883150U
JPS5883150U JP1981176731U JP17673181U JPS5883150U JP S5883150 U JPS5883150 U JP S5883150U JP 1981176731 U JP1981176731 U JP 1981176731U JP 17673181 U JP17673181 U JP 17673181U JP S5883150 U JPS5883150 U JP S5883150U
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
circuit device
conductive film
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1981176731U
Other languages
Japanese (ja)
Inventor
根津　利忠
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP1981176731U priority Critical patent/JPS5883150U/en
Publication of JPS5883150U publication Critical patent/JPS5883150U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来技術でＩＣチップと配線基板の接続状態の
縦断面図、第２図は本考案によるＩＣチップの縦断面図
、第３図は本考案の他の実施例の縦断面図である。 ７．９・・・き裂進行防止の導電膜、８・・・接続ハン
ダ。FIG. 1 is a vertical cross-sectional view of the connection between an IC chip and a wiring board according to the prior art, FIG. 2 is a vertical cross-sectional view of an IC chip according to the present invention, and FIG. 3 is a vertical cross-sectional view of another embodiment of the present invention. be. 7.9... Conductive film to prevent crack progression, 8... Connection solder.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体集積回路と配線基板の接続をフェースダウンボン
ディングしてなる半導体集積回路装置において、前記半
導体集積回路および配線基板の接続端子またはいずれか
一方をあらかじめ接続に必要なサイズで導電膜を形成し
た後、前記導電膜上にこのサイズより小さい導電膜を形
成し、この上に軟ろう付をして、バンプを形成したこと
を特徴とする半導体集積回路装置。In a semiconductor integrated circuit device in which a semiconductor integrated circuit and a wiring board are connected by face-down bonding, after forming a conductive film in a size necessary for connection between the connecting terminals of the semiconductor integrated circuit and the wiring board, or either one of them in advance, A semiconductor integrated circuit device characterized in that a conductive film smaller than this size is formed on the conductive film, and a bump is formed by soft soldering on the conductive film.
JP1981176731U 1981-11-30 1981-11-30 Semiconductor integrated circuit device Pending JPS5883150U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981176731U JPS5883150U (en) 1981-11-30 1981-11-30 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981176731U JPS5883150U (en) 1981-11-30 1981-11-30 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5883150U true JPS5883150U (en) 1983-06-06

Family

ID=29969955

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981176731U Pending JPS5883150U (en) 1981-11-30 1981-11-30 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5883150U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005101614A (en) * 2003-09-23 2005-04-14 Samsung Electronics Co Ltd Reinforced solder bump and method of forming reinforced solder bump structure
JP2015115363A (en) * 2013-12-09 2015-06-22 富士通株式会社 Electronic device and method of manufacturing electronic device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005101614A (en) * 2003-09-23 2005-04-14 Samsung Electronics Co Ltd Reinforced solder bump and method of forming reinforced solder bump structure
JP2015115363A (en) * 2013-12-09 2015-06-22 富士通株式会社 Electronic device and method of manufacturing electronic device

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