JPS60176551U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS60176551U
JPS60176551U JP1984065279U JP6527984U JPS60176551U JP S60176551 U JPS60176551 U JP S60176551U JP 1984065279 U JP1984065279 U JP 1984065279U JP 6527984 U JP6527984 U JP 6527984U JP S60176551 U JPS60176551 U JP S60176551U
Authority
JP
Japan
Prior art keywords
chip
semiconductor device
pad
central
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984065279U
Other languages
Japanese (ja)
Inventor
輝次 佐藤
Original Assignee
日立電線株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日立電線株式会社 filed Critical 日立電線株式会社
Priority to JP1984065279U priority Critical patent/JPS60176551U/en
Publication of JPS60176551U publication Critical patent/JPS60176551U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の半導体装置の縦断面図、第２図は第１図
のＩＣチップの下面図、第３図は本考案の半導体装置の
一実施例を示す縦断面図、第４図は第３図のＩＣチップ
の下面図、第５図は本考案の他の実施例を示す第４図に
相当する下面図である。 １：Ｉｃチップ、２：半田バンプ、３：パッケージ；４
：ＩＣチップパッド、５：放熱用中央半田付パッド、６
：放熱用中央半田バンプ。FIG. 1 is a vertical cross-sectional view of a conventional semiconductor device, FIG. 2 is a bottom view of the IC chip shown in FIG. 1, FIG. 3 is a vertical cross-sectional view showing an embodiment of the semiconductor device of the present invention, and FIG. FIG. 3 is a bottom view of the IC chip, and FIG. 5 is a bottom view corresponding to FIG. 4 showing another embodiment of the present invention. 1: Ic chip, 2: solder bump, 3: package; 4
: IC chip pad, 5: Central soldering pad for heat dissipation, 6
: Central solder bump for heat dissipation.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ＩＣチップが該ＩＣチップのＩＣチップパッドに形成し
た半田バンプによって基板またはパッケージの導体部に
半田付けされているフリップチップ方式の半導体装置に
おいて、前記ＩＣチップの裏面の中央部に放熱用中央半
田付パッドが設けてあり、該放熱用中央半田付パッドの
部分に形成した放熱用中央半田バンプによっても前記基
板またはパッケージに半田付けされている構成としであ
ることを特徴とする半導体装置。In a flip-chip type semiconductor device in which an IC chip is soldered to a conductor part of a substrate or package by solder bumps formed on an IC chip pad of the IC chip, a central solder for heat dissipation is attached to a central part of the back surface of the IC chip. 1. A semiconductor device characterized in that the semiconductor device is provided with a pad, and is also soldered to the substrate or package by a heat dissipating central solder bump formed in a portion of the heat dissipating central solder pad.
JP1984065279U 1984-05-02 1984-05-02 semiconductor equipment Pending JPS60176551U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984065279U JPS60176551U (en) 1984-05-02 1984-05-02 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984065279U JPS60176551U (en) 1984-05-02 1984-05-02 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS60176551U true JPS60176551U (en) 1985-11-22

Family

ID=30597134

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984065279U Pending JPS60176551U (en) 1984-05-02 1984-05-02 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS60176551U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003224158A (en) * 2002-01-25 2003-08-08 Texas Instruments Inc Flip chip for substrate assembly with no bump and polymer layer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003224158A (en) * 2002-01-25 2003-08-08 Texas Instruments Inc Flip chip for substrate assembly with no bump and polymer layer
JP4698125B2 (en) * 2002-01-25 2011-06-08 テキサス インスツルメンツ インコーポレイテッド Flip chip for substrate assembly without bumps and polymer layers

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