JPS6142849U - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS6142849U JPS6142849U JP12705384U JP12705384U JPS6142849U JP S6142849 U JPS6142849 U JP S6142849U JP 12705384 U JP12705384 U JP 12705384U JP 12705384 U JP12705384 U JP 12705384U JP S6142849 U JPS6142849 U JP S6142849U
- Authority
- JP
- Japan
- Prior art keywords
- leadless package
- semiconductor equipment
- integrated circuit
- semiconductor integrated
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案の一実施例によるリードレスパッケージ
の下面図、第2図は第1図のものの端子下面部と印刷配
線板のパッドとの接続態様を示す説明図、第3区は従来
の半導体装置の概要を示す斜視図、第4図は第3図のも
のを印刷配線板に取付けた状態を示す縦断面図、第5図
は第3図のものを下方より示す第1図相当図、第6図は
第5図における端子下面部と印刷配線板のパッドとの接
続態様を示す第2図相当図である。
1,21・・・リードレスパッケージ、3.22・・・
端子、3b,22a・・・下面部、4・・・半導体集積
回路チップ、22b・・・外辺、22c・・・内辺、2
2d・・・側辺。
なお、図中同一符号は同一または相当部分を示す。FIG. 1 is a bottom view of a leadless package according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the connection between the bottom surface of the terminal of the one shown in FIG. 1 and a pad of a printed wiring board, and the third section is a conventional FIG. 4 is a vertical sectional view showing the semiconductor device in FIG. 3 attached to a printed wiring board, and FIG. 5 is equivalent to FIG. 1 showing the semiconductor device in FIG. 3 from below. FIG. 6 is a view corresponding to FIG. 2 showing the manner of connection between the lower surface portion of the terminal in FIG. 5 and the pad of the printed wiring board. 1,21...leadless package, 3.22...
Terminal, 3b, 22a... Bottom surface part, 4... Semiconductor integrated circuit chip, 22b... Outer side, 22c... Inner side, 2
2d...Side side. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
記半導体集積回路と外部との電気的接続を行なう多数の
端子が設けられた直方体状のリードレスパッケージを備
え、上記リードレスパツケージの各端子の幅を、リード
レスパッケージ周辺側よりも内方側が狭くなるよう設定
したことを特徴とする半導体装置。- A rectangular parallelepiped leadless package that accommodates a semiconductor integrated circuit chip and is provided with a number of terminals on its periphery for electrically connecting the semiconductor integrated circuit to the outside, the width of each terminal of the leadless package A semiconductor device characterized in that the inner side of the leadless package is narrower than the peripheral side of the leadless package.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12705384U JPS6142849U (en) | 1984-08-22 | 1984-08-22 | semiconductor equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12705384U JPS6142849U (en) | 1984-08-22 | 1984-08-22 | semiconductor equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6142849U true JPS6142849U (en) | 1986-03-19 |
Family
ID=30685703
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12705384U Pending JPS6142849U (en) | 1984-08-22 | 1984-08-22 | semiconductor equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6142849U (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016219624A (en) * | 2015-05-21 | 2016-12-22 | 京セラ株式会社 | Laminated capacitor and mounting structure thereof |
JP2016219741A (en) * | 2015-05-26 | 2016-12-22 | 京セラ株式会社 | Laminated capacitor and mounting structure thereof |
-
1984
- 1984-08-22 JP JP12705384U patent/JPS6142849U/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016219624A (en) * | 2015-05-21 | 2016-12-22 | 京セラ株式会社 | Laminated capacitor and mounting structure thereof |
JP2016219741A (en) * | 2015-05-26 | 2016-12-22 | 京セラ株式会社 | Laminated capacitor and mounting structure thereof |
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