JPS6210469U - - Google Patents
Info
- Publication number
- JPS6210469U JPS6210469U JP10097385U JP10097385U JPS6210469U JP S6210469 U JPS6210469 U JP S6210469U JP 10097385 U JP10097385 U JP 10097385U JP 10097385 U JP10097385 U JP 10097385U JP S6210469 U JPS6210469 U JP S6210469U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- printed circuit
- mini
- mounting structure
- flat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
第１図は本考案の一実施例を示す斜視図、第２
図は同側面図、第３図は従来のプリント基板実装
構造を示す斜視図、第４図および第５図はそれぞ
れ半田付け過程を示す側面図である。
１…ミニフラツトＩＣ、２…プリント基板、３
ａ，３ａ′…ランド、１ａ，１ａ′…リード線、
４，４′…ダミーランド、５…接着剤、６…半田
ブリツジ、７…半田噴流、Ａ…半田槽を流す方向
を示す矢印。
Fig. 1 is a perspective view showing one embodiment of the present invention;
3 is a perspective view showing a conventional printed circuit board mounting structure, and FIGS. 4 and 5 are side views showing the soldering process, respectively. 1...Mini flat IC, 2...Printed circuit board, 3
a, 3a'... land, 1a, 1a'... lead wire,
4, 4'...Dummy land, 5...Adhesive, 6...Solder bridge, 7...Solder jet, A...Arrow indicating the direction of flowing the solder bath.
Claims (1)
るプリント基板実装構造において、前記ミニフラ
ツトＩＣのリード線を接合する前記プリント基板
のランド部に、リード線間隔と同じ配列で１対の
ダミーランドを設けたことを特徴とするプリント
基板実装構造。 A printed circuit board mounting structure in which a mini-flat IC is soldered to a printed circuit board, characterized in that a pair of dummy lands are provided in the land portion of the printed circuit board to which the lead wires of the mini-flat IC are bonded in the same arrangement as the lead wire spacing. Printed circuit board mounting structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10097385U JPS6210469U (en) | 1985-07-02 | 1985-07-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10097385U JPS6210469U (en) | 1985-07-02 | 1985-07-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6210469U true JPS6210469U (en) | 1987-01-22 |
Family
ID=30971286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10097385U Pending JPS6210469U (en) | 1985-07-02 | 1985-07-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6210469U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63213994A (en) * | 1987-03-03 | 1988-09-06 | 松下電器産業株式会社 | Method of dip soldering of four-directional leaded flat package ic |
| JPH0254598A (en) * | 1988-08-18 | 1990-02-23 | Matsushita Electric Ind Co Ltd | Manufacture of mounted printed board of integrated circuit component |
| JPH0415264U (en) * | 1990-05-29 | 1992-02-06 |
-
1985
- 1985-07-02 JP JP10097385U patent/JPS6210469U/ja active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63213994A (en) * | 1987-03-03 | 1988-09-06 | 松下電器産業株式会社 | Method of dip soldering of four-directional leaded flat package ic |
| JPH0254598A (en) * | 1988-08-18 | 1990-02-23 | Matsushita Electric Ind Co Ltd | Manufacture of mounted printed board of integrated circuit component |
| JPH0415264U (en) * | 1990-05-29 | 1992-02-06 |
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