JPS6292682U - - Google Patents

Info

Publication number
JPS6292682U
JPS6292682U JP18565285U JP18565285U JPS6292682U JP S6292682 U JPS6292682 U JP S6292682U JP 18565285 U JP18565285 U JP 18565285U JP 18565285 U JP18565285 U JP 18565285U JP S6292682 U JPS6292682 U JP S6292682U
Authority
JP
Japan
Prior art keywords
wiring board
printed wiring
dual inline
inline package
lead terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18565285U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18565285U priority Critical patent/JPS6292682U/ja
Publication of JPS6292682U publication Critical patent/JPS6292682U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案のデユアルインラインパツケ
ージICを示す斜視図、第2図はこの考案の一実
施例を示す立面図、第3図及び第4図は従来の構
造を示す図である。 1はデユアルインラインパツケージICの容器
、2はリード端子、3は印刷配線板、4は半田接
続部。尚、各図中同一符号は同一又は相当部分を
示す。
FIG. 1 is a perspective view showing a dual in-line package IC of this invention, FIG. 2 is an elevational view showing an embodiment of this invention, and FIGS. 3 and 4 are views showing a conventional structure. 1 is a dual inline package IC container, 2 is a lead terminal, 3 is a printed wiring board, and 4 is a solder connection part. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】 デユアルインラインパツケージICが装着され
る印刷配線板において、 デユアルインラインパツケージICの各リード
端子を2個所で折り曲げ、上記各リード端子の先
端部分が当該デユアルインラインパツケージIC
の容器の底面より下方にあつて上記先端部分の方
向が上記底面に平行になるようにして、印刷配線
板上の電子部品取付けランドに半田付けすること
を特徴とする印刷配線板。
[Claim for Utility Model Registration] In a printed wiring board to which a dual inline package IC is mounted, each lead terminal of the dual inline package IC is bent at two places, and the tip of each lead terminal is connected to the dual inline package IC.
1. A printed wiring board, wherein the printed wiring board is soldered to an electronic component mounting land on the printed wiring board such that the tip portion is located below the bottom surface of the container and the direction of the tip portion is parallel to the bottom surface.
JP18565285U 1985-12-02 1985-12-02 Pending JPS6292682U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18565285U JPS6292682U (en) 1985-12-02 1985-12-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18565285U JPS6292682U (en) 1985-12-02 1985-12-02

Publications (1)

Publication Number Publication Date
JPS6292682U true JPS6292682U (en) 1987-06-13

Family

ID=31134480

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18565285U Pending JPS6292682U (en) 1985-12-02 1985-12-02

Country Status (1)

Country Link
JP (1) JPS6292682U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014053344A (en) * 2012-09-05 2014-03-20 Renesas Electronics Corp Electronic apparatus and semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014053344A (en) * 2012-09-05 2014-03-20 Renesas Electronics Corp Electronic apparatus and semiconductor device

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