JPS6212982U - - Google Patents
Info
- Publication number
- JPS6212982U JPS6212982U JP10461585U JP10461585U JPS6212982U JP S6212982 U JPS6212982 U JP S6212982U JP 10461585 U JP10461585 U JP 10461585U JP 10461585 U JP10461585 U JP 10461585U JP S6212982 U JPS6212982 U JP S6212982U
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- printed wiring
- electronic component
- equal intervals
- connecting terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 239000011888 foil Substances 0.000 claims description 3
- 238000005476 soldering Methods 0.000 claims 2
Description
第１図ａは本考案の一実施例を示す正面図、第
１図ｂはその部分拡大斜視図、第２図は一般的な
フラツトバツクＩＣを印刷配線基板へ搭載するこ
とを示す説明用斜視図、第３図ａは従来のはんだ
ペースト塗布例を示す正面図、第３図ｂはその部
分拡大斜視図、第４図ａは従来のはんだペースト
塗布例を示す正面図、第４図ｂはその部分拡大斜
視図、第５図ａは一般的なフラツトパツクＩＣが
印刷配線板にはんだ付けされた状態を示す正面図
、第５図ｂはその部分拡大斜視図である。
１……印刷配線基板、２……面実装部品、３…
…接続端子、４……導電箔、５……はんだ、６…
…はんだペースト、Ａ……はんだによる短絡。
FIG. 1a is a front view showing one embodiment of the present invention, FIG. 1b is a partially enlarged perspective view thereof, and FIG. 2 is an explanatory perspective view showing mounting of a general flat back IC on a printed wiring board. , Fig. 3a is a front view showing an example of conventional solder paste application, Fig. 3b is a partially enlarged perspective view thereof, Fig. 4a is a front view showing an example of conventional solder paste application, and Fig. 4b is its partial enlarged perspective view. FIG. 5a is a front view showing a general flat pack IC soldered to a printed wiring board, and FIG. 5b is a partially enlarged perspective view thereof. 1...Printed wiring board, 2...Surface mount components, 3...
... Connection terminal, 4 ... Conductive foil, 5 ... Solder, 6 ...
...Solder paste, A...Short circuit due to solder.
Claims (1)
続端子を有し面実装される電子部品を印刷配線基
板上に搭載し、前記電子部品の多数の接続端子を
前記印刷配線基板上に等間隔で配設された導電箔
のそれぞれにリフロー半田付けによつて固定する
ものにおいて、前記印刷配線基板上の導電箔群に
対してリフローはんだ付けのためのはんだペース
トを千鳥状に塗布したことを特徴とする印刷配線
基板。 A surface-mounted electronic component having a large number of connecting terminals led out from the end surface of the main body at equal intervals is mounted on a printed wiring board, and the numerous connecting terminals of the electronic component are mounted at equal intervals on the printed wiring board. in which each of the conductive foils arranged on the printed circuit board is fixed by reflow soldering, characterized in that a solder paste for reflow soldering is applied in a staggered manner to the group of conductive foils on the printed wiring board. Printed wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10461585U JPS6212982U (en) | 1985-07-09 | 1985-07-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10461585U JPS6212982U (en) | 1985-07-09 | 1985-07-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6212982U true JPS6212982U (en) | 1987-01-26 |
Family
ID=30978271
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10461585U Pending JPS6212982U (en) | 1985-07-09 | 1985-07-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6212982U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0269992A (en) * | 1988-09-05 | 1990-03-08 | Fujitsu Ltd | Method of soldering lead of surface mounting part |
-
1985
- 1985-07-09 JP JP10461585U patent/JPS6212982U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0269992A (en) * | 1988-09-05 | 1990-03-08 | Fujitsu Ltd | Method of soldering lead of surface mounting part |
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