JPS62158829U - - Google Patents
Info
- Publication number
- JPS62158829U JPS62158829U JP4673786U JP4673786U JPS62158829U JP S62158829 U JPS62158829 U JP S62158829U JP 4673786 U JP4673786 U JP 4673786U JP 4673786 U JP4673786 U JP 4673786U JP S62158829 U JPS62158829 U JP S62158829U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- opening
- view
- chip
- superimposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Description
第１図は本考案の多層式回路基板の縦断面図、
第２図は第１図の分解縦断面図、第３図は上部回
路基板の平面図、第４図は第３図の―線断面
図、第５図は下部回路基板の平面図、第６図は第
５図の―線断面図である。
尚、図中、Ａ：多層式回路基板、１：上部回路
基板、２：下部回路基板、３：リードピン、５：
開口部、７：ＩＣチツプ、１０：マウント部を示
す。
FIG. 1 is a vertical cross-sectional view of the multilayer circuit board of the present invention.
Figure 2 is an exploded longitudinal sectional view of Figure 1, Figure 3 is a plan view of the upper circuit board, Figure 4 is a sectional view taken along the line - - in Figure 3, Figure 5 is a plan view of the lower circuit board, and Figure 6 is a plan view of the lower circuit board. The figure is a sectional view taken along the line -- in FIG. In the figure, A: multilayer circuit board, 1: upper circuit board, 2: lower circuit board, 3: lead pin, 5:
Opening part, 7: IC chip, 10: mount part are shown.
Claims (1)
した上部回路基板を重ね合わせ、これらをリード
ピンで接合すると共に、前記開口部により形成さ
れたマウント部にＩＣチツプを搭載して形成した
多層式回路基板。 An upper circuit board with an opening in the center is superimposed on the upper surface of the lower circuit board, and these are joined with lead pins, and an IC chip is mounted on the mount formed by the opening. formula circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4673786U JPS62158829U (en) | 1986-03-28 | 1986-03-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4673786U JPS62158829U (en) | 1986-03-28 | 1986-03-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62158829U true JPS62158829U (en) | 1987-10-08 |
Family
ID=30866675
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4673786U Pending JPS62158829U (en) | 1986-03-28 | 1986-03-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62158829U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05121859A (en) * | 1991-10-25 | 1993-05-18 | Fujitsu Ltd | Wiring connection method |
-
1986
- 1986-03-28 JP JP4673786U patent/JPS62158829U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05121859A (en) * | 1991-10-25 | 1993-05-18 | Fujitsu Ltd | Wiring connection method |