JPS63140645U - - Google Patents

Info

Publication number
JPS63140645U
JPS63140645U JP3265687U JP3265687U JPS63140645U JP S63140645 U JPS63140645 U JP S63140645U JP 3265687 U JP3265687 U JP 3265687U JP 3265687 U JP3265687 U JP 3265687U JP S63140645 U JPS63140645 U JP S63140645U
Authority
JP
Japan
Prior art keywords
package
pins
board
packaging
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3265687U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3265687U priority Critical patent/JPS63140645U/ja
Publication of JPS63140645U publication Critical patent/JPS63140645U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案によるICパツケージの外形図
、第2図は本考案によるICパツケージの基板上
への実装図、第3図は第2図のA―B線断面図、
第4図は本考案によるICパツケージの実施例2
の外形図、第5図は実施例2のICパツケージの
基板上への実装図、第6図は第5図のA―B線断
面図、第7図、第8図および第9図は従来のパツ
ケージの図である。 1……ICパツケージ本体、2……ICパツケ
ージの底面に構成したピン、3……ICパツケー
ジの側面に構成したピン、4……ICパツケージ
を実装するための基板、5……ICパツケージの
上面に構成したピン、6……4とは別のICパツ
ケージを実装するための基板。
FIG. 1 is an external view of the IC package according to the present invention, FIG. 2 is a diagram of the IC package according to the present invention mounted on a board, and FIG. 3 is a cross-sectional view taken along the line AB in FIG. 2.
Figure 4 shows Example 2 of the IC package according to the present invention.
, FIG. 5 is a diagram of the IC package of Example 2 mounted on a board, FIG. 6 is a sectional view taken along line A-B in FIG. 5, and FIGS. 7, 8, and 9 are conventional FIG. 1... IC package body, 2... Pins configured on the bottom of the IC package, 3... Pins configured on the side of the IC package, 4... Board for mounting the IC package, 5... Top surface of the IC package A board for mounting an IC package different from pins 6...4.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 底面と、少くとも側面に、各々外部との電気的
接続を行うピンを構成することを特徴とするIC
パツケージ。
An IC characterized in that pins for electrical connection with the outside are formed on the bottom surface and at least the side surfaces, respectively.
Packaging.
JP3265687U 1987-03-05 1987-03-05 Pending JPS63140645U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3265687U JPS63140645U (en) 1987-03-05 1987-03-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3265687U JPS63140645U (en) 1987-03-05 1987-03-05

Publications (1)

Publication Number Publication Date
JPS63140645U true JPS63140645U (en) 1988-09-16

Family

ID=30839543

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3265687U Pending JPS63140645U (en) 1987-03-05 1987-03-05

Country Status (1)

Country Link
JP (1) JPS63140645U (en)

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