JPH01235356A - Module board - Google Patents
Module boardInfo
- Publication number
- JPH01235356A JPH01235356A JP63063854A JP6385488A JPH01235356A JP H01235356 A JPH01235356 A JP H01235356A JP 63063854 A JP63063854 A JP 63063854A JP 6385488 A JP6385488 A JP 6385488A JP H01235356 A JPH01235356 A JP H01235356A
- Authority
- JP
- Japan
- Prior art keywords
- terminals
- terminal
- hole
- external extraction
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000011347 resin Substances 0.000 abstract description 7
- 229920005989 resin Polymers 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 7
- 239000000853 adhesive Substances 0.000 abstract description 5
- 230000001070 adhesive effect Effects 0.000 abstract description 5
- 238000000605 extraction Methods 0.000 abstract 6
- 239000011162 core material Substances 0.000 description 4
- 239000005001 laminate film Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 230000000276 sedentary effect Effects 0.000 description 1
- 235000014347 soups Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【発明の詳細な説明】
〔座業上の利用分野〕
本発明はモジュール基板に関し、特にＩＣカード等に搭
載する超薄型モジュールに用いるモジュール基板に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of sedentary use] The present invention relates to a module substrate, and particularly to a module substrate used for an ultra-thin module mounted on an IC card or the like.
従来、この植のモジュール基板は、第５図及び第６図に
示すように、絶縁性基板１の上面に設けた半導体チップ
１３が入るキャビティ部１２と樹脂ダム１１と複数の配
線層１０ｔ−有し、更に絶縁性基板１の下面に設けた外
部導出用端子３ｔ−有し、外部導出用端子３は対応する
配線層ｌＯとスルホール２によって電気的に接続され、
外部導出用端子３上に突起状端子５ａを形成していた。Conventionally, as shown in FIGS. 5 and 6, this type of module board includes a cavity 12 provided on the upper surface of an insulating substrate 1 into which a semiconductor chip 13 is placed, a resin dam 11, and a plurality of wiring layers 10t. Furthermore, the insulating substrate 1 has an external lead-out terminal 3t- provided on the lower surface, and the external lead-out terminal 3 is electrically connected to the corresponding wiring layer 1O by the through hole 2.
A protruding terminal 5a was formed on the external lead-out terminal 3.
半導体チップ１３は絶縁性基板ｌのキャビティ部１２に
Ａｇペースト等からなる接１剤１６により固着され、半
導体チップ１３の電極端子と配線層ｌＯの一方であるポ
ンディングパッド７とをポンディングワイヤ８でボッデ
ィングされ、更に、封止用樹脂１５が半導体チップ１３
を覆って樹脂ダム１１に充填されて超薄型のモジュール
を形成していた。The semiconductor chip 13 is fixed to the cavity part 12 of the insulating substrate l with a bonding agent 16 made of Ag paste or the like, and the electrode terminal of the semiconductor chip 13 and the bonding pad 7, which is one of the wiring layers lO, are connected by a bonding wire 8. Further, the sealing resin 15 is bonded to the semiconductor chip 13.
was filled into the resin dam 11 to form an ultra-thin module.
ＩＣカードに搭載する場合は、上記のモジュール金コア
材に挿入し表面に突起状端子の孔を設けたラミネートフ
ィルムで両面をラミネートする。When mounting on an IC card, the module is inserted into the gold core material described above and both sides are laminated with a laminate film having holes for protruding terminals on the surface.
上述した従来のモジュール基板は、外部導出用端子にス
ルホールが存在するので、スルホールの穴とスルホール
形成時のめっきによシ、スルホールランド９（第６図参
照）が盛上って外部導出用端子表面に凹凸ができ、ラミ
ネートを施こした時に凹凸が境われて外観を損い、かつ
、スルーホールに汚物が侵入して不良発生の原因になる
という欠点がある。In the conventional module board described above, there is a through hole in the terminal for external lead-out, so due to the through-hole hole and the plating during the formation of the through-hole, the through-hole land 9 (see Figure 6) swells up and becomes the terminal for external lead-out. There are disadvantages in that the surface is uneven, and when laminated, the unevenness is bordered and spoils the appearance, and dirt can enter the through holes, causing defects.
本発明のモジュール基板は、絶縁性基板と、該絶縁性基
板の一方の面に形成された配線層と、前記絶縁性基板の
他方の面に形成され前記配線層とスルーホールによ多接
続される外部導出用端子と、該外部導出用端子の表面に
前記スルーホールを覆って形成された突起状端子とを含
んで構成される。The module board of the present invention includes an insulating substrate, a wiring layer formed on one surface of the insulating substrate, and a wiring layer formed on the other surface of the insulating substrate and connected to the wiring layer through through holes. The terminal includes an external lead-out terminal, and a protruding terminal formed on the surface of the external lead-out terminal so as to cover the through hole.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図及び第２図は本発明の一実施例の断面図及び平面
図である。1 and 2 are a sectional view and a plan view of an embodiment of the present invention.
第１図及び第２図に示すように、絶縁性基板ｌと、絶縁
性基板ｌの上面に設けた半導体チップ１３が入るキャビ
ティ部１２と樹脂ダム１１と複数の配線層ｌＯを有し、
更に、絶縁性基板１の下面に設けた配線層１０に対応す
る外部導出用端子３を有し、外部導出用端子３は対応す
る配線層１０とスルーホール２によって電気的に接続ち
れ、スルーホール２の外部導出用端子３表面のスルーホ
ールランド９ｔ＝って外部導出用端子３上に突起状端子
５を設けている。突起状端子５は表面に金属めっき６７
に施しＡｇペーストのような導電性の接着剤４により外
部導出用端子３に固層される。As shown in FIGS. 1 and 2, it has an insulating substrate l, a cavity part 12 into which a semiconductor chip 13 provided on the upper surface of the insulating substrate l is inserted, a resin dam 11, and a plurality of wiring layers lO,
Furthermore, it has an external lead-out terminal 3 corresponding to the wiring layer 10 provided on the lower surface of the insulating substrate 1, and the external lead-out terminal 3 is electrically connected to the corresponding wiring layer 10 by the through hole 2, and the through hole 2 is electrically connected to the corresponding wiring layer 10. A through-hole land 9t on the surface of the external lead-out terminal 3 of the hole 2 is provided with a protruding terminal 5 on the external lead-out terminal 3. The protruding terminal 5 has metal plating 67 on its surface.
The conductive adhesive 4 such as Ag paste is applied to the external lead terminal 3 and fixed thereto.
このように構成したモジュール基板を用いて前述した従
来と同様に超薄型のモジュールヲ裂造するＯ
第３図は第１図の実施例を用いたモジュールを搭載する
ＩＣカードの断面図である。Using the module board configured in this manner, an ultra-thin module is fabricated in the same manner as in the conventional method described above. Figure 3 is a cross-sectional view of an IC card equipped with a module using the embodiment shown in Figure 1. .
第３図に示すように、モジュール１４ｉコア材１７に挿
入し表面に突起状端子５の孔を設けたラミネートフィル
ム１８ａとラミネートフィルム１８ｂとで挾んで両面を
ラミネートする。As shown in FIG. 3, the module 14i is inserted into the core material 17 and sandwiched between a laminate film 18a and a laminate film 18b having holes for the protruding terminals 5 on their surfaces, and both sides are laminated.
第４囚は本発明の第２の実施例に用いる突起状端子の断
面図である。The fourth figure is a sectional view of a protruding terminal used in the second embodiment of the present invention.
第４図に示すように、第２の実施例は突起状端子にスル
ーホールランド９を逃げる凹部を設けた突起状端子５ａ
を用いている。As shown in FIG. 4, the second embodiment is a protruding terminal 5a in which a concave portion for escaping the through-hole land 9 is provided in the protruding terminal.
is used.
第２の実施例では、突起状端子にスルーホールランド９
の逃げのための凹部を設けるため、突起状端子が傾いて
接着嘔れることを防止できる利点がある。In the second embodiment, a through-hole land 9 is provided on the protruding terminal.
Since the concave portion is provided for escape, there is an advantage that it is possible to prevent the protruding terminal from being tilted and the adhesive from collapsing.
以上説明したように本発明は、外部導出用内子のスルホ
ール金覆う位置に突起状端子を設けることによシ、外部
導出用端子表面のスルホールの凹凸部トスルーホール穴
トｆ無＜Ｌ、スルーホールに汚物が侵入することによる
これを用いたモジュールの性能劣化を防止し、かつ、外
観を向上できる効果がある。As explained above, the present invention provides a projecting terminal at a position covering the through-hole metal of the inner core for external lead-out. This has the effect of preventing performance deterioration of the module using this due to dirt entering the hole, and improving the appearance.
第１図及び第２図はそれぞれ本発明の第１の実施例の断
面図及び平面図、第３図は第１図の実施例を用いたモジ
ュールを搭載するＩＣカードの断面図、第４図は本発明
の第２の実施例に用いる突ｌ・・・・・・絶縁性基板、
２・・・・・・スルーホール、３・・・・・・外部導出
用端子、４・・・・・・接着剤、５．５ａ＊５ｂ・・・
・・・突起状端子、６・・・・・・金属めっき、７・・
・・・・ポンディングパッド、８・・・・・・ポンディ
ングワイヤ、９・・・・・・スルーホールランド、１ｏ
・山・・配線層、１１・・・・・・樹脂ダム、１２・川
・・キャビティ部、１３・・・・・・半導体チップ、１
４・・印・モジュール、１５・・・・・・封止用樹脂、
１６・・・・・・接着剤、１７・・・・・・コア材、１
８．１．１８ｂ・・・・・・ラミネートフィルム。
代理人 弁理士 内 原 音
ｂ
１Ｍａｆ！墨板、 ’ｌ スＬ−汁、４．３％ａＰＩ４
’ＬＦＫ！ｒＭｈ４ｔ／Ｊ５突赳４天ｍ’ｒ、 ６Ｍ
ｈｔｎ−５７＃、７＞テ；；７ｈ°’、ｆ、ｇｒＴ’、
” 私ニア ’７４ｔ’９ 又几−ホーｈｉ；Ｆ、１０
に’！ｒ裟督、Ｊ１４ｔａダム、１２キ記’ｉｓ ｕ。
１３千講１体→ツブ、１５１１止阻剰凰、１を浸漬ｐ１
も ２ 図
第 ３ 図
的 ４ 閏1 and 2 are a sectional view and a plan view, respectively, of a first embodiment of the present invention, FIG. 3 is a sectional view of an IC card equipped with a module using the embodiment of FIG. 1, and FIG. 4 is an insulating substrate used in the second embodiment of the present invention;
2... Through hole, 3... External lead-out terminal, 4... Adhesive, 5.5a*5b...
...Protruding terminal, 6...Metal plating, 7...
...Ponding pad, 8...Ponding wire, 9...Through hole land, 1o
・Mountain...Wiring layer, 11...Resin dam, 12.River...Cavity part, 13...Semiconductor chip, 1
4... mark module, 15... sealing resin,
16... Adhesive, 17... Core material, 1
8.1.18b... Laminate film. Agent Patent Attorney Uchihara Otob 1Maf! Ink board, 'l soup, 4.3% aPI4
'LFK! rMh4t/J5赵赳4天m'r, 6M
htn-57#, 7>te;;7h°', f, grT',
” Me near '74t'9 Mata - ho hi; F, 10
Ni'! Director, J14ta Dam, 12 Ki'is u. 13,000 lectures → Tsubu, 1511 stop-stopping, 1 soaked p1
2 Figure 3 Figure 4 Leap
Claims (1)
配線層と、前記絶縁性基板の他方の面に形成され前記配
線層とスルーホールにより接続される外部導出用端子と
、該外部導出用端子の表面に前記スルーホールを覆って
形成された突起状端子とを含むことを特徴とするモジュ
ール基板。an insulating substrate, a wiring layer formed on one surface of the insulating substrate, an external lead-out terminal formed on the other surface of the insulating substrate and connected to the wiring layer through a through hole, A module board comprising: a protruding terminal formed on the surface of the lead-out terminal so as to cover the through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63063854A JPH01235356A (en) | 1988-03-16 | 1988-03-16 | Module board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63063854A JPH01235356A (en) | 1988-03-16 | 1988-03-16 | Module board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01235356A true JPH01235356A (en) | 1989-09-20 |
Family
ID=13241339
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63063854A Pending JPH01235356A (en) | 1988-03-16 | 1988-03-16 | Module board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01235356A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0292936U (en) * | 1989-01-09 | 1990-07-24 | ||
| US5668406A (en) * | 1994-05-31 | 1997-09-16 | Nec Corporation | Semiconductor device having shielding structure made of electrically conductive paste |
-
1988
- 1988-03-16 JP JP63063854A patent/JPH01235356A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0292936U (en) * | 1989-01-09 | 1990-07-24 | ||
| US5668406A (en) * | 1994-05-31 | 1997-09-16 | Nec Corporation | Semiconductor device having shielding structure made of electrically conductive paste |
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