JPH0375540U - - Google Patents
Info
- Publication number
- JPH0375540U JPH0375540U JP13679489U JP13679489U JPH0375540U JP H0375540 U JPH0375540 U JP H0375540U JP 13679489 U JP13679489 U JP 13679489U JP 13679489 U JP13679489 U JP 13679489U JP H0375540 U JPH0375540 U JP H0375540U
- Authority
- JP
- Japan
- Prior art keywords
- recess
- metal plate
- exposed
- mounting board
- semiconductor mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000011347 resin Substances 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims 5
- 229910052751 metal Inorganic materials 0.000 claims 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims 1
- 239000004020 conductor Substances 0.000 claims 1
- 239000011889 copper foil Substances 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 229910052759 nickel Inorganic materials 0.000 claims 1
- 238000007747 plating Methods 0.000 claims 1
- 238000007789 sealing Methods 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案による半導体搭載用基板の製造
工程を示した図で、第２図は本考案による基板に
半導体チツプを搭載し樹脂封止したパツケージの
概念を示す断面図である。第３図は従来の半導体
搭載用基板に半導体チツプを搭載し樹脂封止した
パツケージの概念を示す断面図である。
FIG. 1 is a diagram showing the manufacturing process of a substrate for mounting a semiconductor according to the present invention, and FIG. 2 is a cross-sectional view showing the concept of a package in which a semiconductor chip is mounted on a substrate according to the present invention and sealed with resin. FIG. 3 is a sectional view showing the concept of a package in which a semiconductor chip is mounted on a conventional semiconductor mounting substrate and sealed with resin.
Claims (1)
チツプを搭載した後、凹部周辺のボンデイングパ
ツドを取り囲む位置に樹脂枠を貼りつけて封止樹
脂を注入す半導体搭載用基板において、前記凹部
を形成する予定位置に金属板を載置し銅箔および
プリプレグと共に積層して、予め金属板を埋入し
た銅張積層板を形成した後、スルーホールおよび
回路パターンを形成し、ソルダーレジストを印刷
し露出している導体部分にニツケル・金メツキを
施した後、前記金属板の上部より該金属板の上部
に貫入し、もしくは上面の位置まで座ぐり加工し
て、少なくとも底面には金属板が露出した凹部を
形成したことを特徴とする半導体搭載用基板。 A recess is provided in a printed circuit board, a semiconductor chip is mounted in the recess, a resin frame is attached to a position surrounding the bonding pad around the recess, and a sealing resin is injected.The recess is formed in a semiconductor mounting board. A metal plate is placed in the planned position and laminated with copper foil and prepreg to form a copper-clad laminate with the metal plate embedded in advance.Through holes and circuit patterns are formed, and solder resist is printed and exposed. After applying nickel/gold plating to the conductor part, the upper part of the metal plate is penetrated from the upper part of the metal plate, or counterbore is processed to the position of the top surface, so that the metal plate is exposed at least on the bottom surface. A semiconductor mounting board characterized by having a recess formed therein.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13679489U JPH0375540U (en) | 1989-11-28 | 1989-11-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13679489U JPH0375540U (en) | 1989-11-28 | 1989-11-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0375540U true JPH0375540U (en) | 1991-07-29 |
Family
ID=31683983
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13679489U Pending JPH0375540U (en) | 1989-11-28 | 1989-11-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0375540U (en) |
-
1989
- 1989-11-28 JP JP13679489U patent/JPH0375540U/ja active Pending
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