JPS54148480A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS54148480A
JPS54148480A JP5781078A JP5781078A JPS54148480A JP S54148480 A JPS54148480 A JP S54148480A JP 5781078 A JP5781078 A JP 5781078A JP 5781078 A JP5781078 A JP 5781078A JP S54148480 A JPS54148480 A JP S54148480A
Authority
JP
Japan
Prior art keywords
frame
layer
lead
conductor
lamination
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5781078A
Other languages
Japanese (ja)
Inventor
Katsuhiko Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5781078A priority Critical patent/JPS54148480A/en
Publication of JPS54148480A publication Critical patent/JPS54148480A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Abstract

PURPOSE: To eliminate the fragileness breakdown caused by the difference of the heat expansion by providing the welding conductor layer on the upper surface via the ceramic frame instead of the metal sealed frame when forming the lamination alumina ceramic substrate.
CONSTITUTION: Ceramic frame 12 is attached to upper surface 14 of lamination ceramic substrate 21 by surrounding the concavity which is to be used as semiconductor element sealing part 2. Then the W paste is printed on the upper surface of part 2, internal lead 3, external lead soldering part 5 leading from lead 3 via concucting layer 13 and frame 12 each, thus forming the metalized layer through burning. The Ni plating is applied there, and external lead 7 is attached to part 5 via Ag-Cu solder material. At the same time, 3-layer structure cap welded conductor 15 composed of the metalized layer, Ni plating layer and Ag-Cu solder material is formed on the upper surface of frame 12. The package is formed in such structure with semiconductor element 8 adhered. Then the electrode and lead 3 are combined with metal thin wire 9, and metal cap 21 is put onto frame 12 to be welded to conductor 15.
COPYRIGHT: (C)1979,JPO&Japio
JP5781078A 1978-05-15 1978-05-15 Semiconductor device Pending JPS54148480A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5781078A JPS54148480A (en) 1978-05-15 1978-05-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5781078A JPS54148480A (en) 1978-05-15 1978-05-15 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS54148480A true JPS54148480A (en) 1979-11-20

Family

ID=13066270

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5781078A Pending JPS54148480A (en) 1978-05-15 1978-05-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS54148480A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0359639U (en) * 1989-10-13 1991-06-12

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0359639U (en) * 1989-10-13 1991-06-12

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