JPS54102969A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS54102969A
JPS54102969A JP1033478A JP1033478A JPS54102969A JP S54102969 A JPS54102969 A JP S54102969A JP 1033478 A JP1033478 A JP 1033478A JP 1033478 A JP1033478 A JP 1033478A JP S54102969 A JPS54102969 A JP S54102969A
Authority
JP
Japan
Prior art keywords
fusing point
point glass
low fusing
semiconductor device
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1033478A
Other languages
Japanese (ja)
Other versions
JPS6043660B2 (en
Inventor
Katsuhiko Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1033478A priority Critical patent/JPS6043660B2/en
Publication of JPS54102969A publication Critical patent/JPS54102969A/en
Publication of JPS6043660B2 publication Critical patent/JPS6043660B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To prevent the short circuit of the metal thin wire as well as to increase the tensile strength, and thus to enhance both the working efficiency and the reliability for the low fusing point glass sealing type semiconductor device by mounting the small chip to the large island diameter container for the semiconductor.
CONSTITUTION: In the low fusing point glass sealing type semiconductor device, metalized layer 17 which is to become island part 13 is formed via the AU paste or the like at the concave part nearly in the center of substrate 11 composed of ceramics, metal and the like in order to fix chip 12. Then internal lead 14 formed by arranging the lead frames radially is piled on substrate 11 from the peripheral part of part 13 to be adhered by low fusing point glass 15 corresponding to the heat expansion of each material, and the tip of lead 14 and the chip electrode are connected to each other via metal thin wire 16. Cap 18 made of ceramics or metal and featuring a shallow depth at the center part is glazed by the low fusing point glass corresponding to the heat expansion of each material.
COPYRIGHT: (C)1979,JPO&Japio
JP1033478A 1978-01-31 1978-01-31 semiconductor equipment Expired JPS6043660B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1033478A JPS6043660B2 (en) 1978-01-31 1978-01-31 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1033478A JPS6043660B2 (en) 1978-01-31 1978-01-31 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS54102969A true JPS54102969A (en) 1979-08-13
JPS6043660B2 JPS6043660B2 (en) 1985-09-30

Family

ID=11747293

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1033478A Expired JPS6043660B2 (en) 1978-01-31 1978-01-31 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS6043660B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007081127A (en) * 2005-09-14 2007-03-29 Sharp Corp Semiconductor device and method of manufacturing same
US7821129B2 (en) * 2004-12-08 2010-10-26 Agilent Technologies, Inc. Low cost hermetic ceramic microcircuit package

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES2848716T3 (en) 2016-10-10 2021-08-11 Akk Gmbh Composite panel with barrier layer and procedure for the manufacture of a letterpress printing plate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7821129B2 (en) * 2004-12-08 2010-10-26 Agilent Technologies, Inc. Low cost hermetic ceramic microcircuit package
JP2007081127A (en) * 2005-09-14 2007-03-29 Sharp Corp Semiconductor device and method of manufacturing same

Also Published As

Publication number Publication date
JPS6043660B2 (en) 1985-09-30

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