JPS6043660B2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS6043660B2 JPS6043660B2 JP1033478A JP1033478A JPS6043660B2 JP S6043660 B2 JPS6043660 B2 JP S6043660B2 JP 1033478 A JP1033478 A JP 1033478A JP 1033478 A JP1033478 A JP 1033478A JP S6043660 B2 JPS6043660 B2 JP S6043660B2
- Authority
- JP
- Japan
- Prior art keywords
- point glass
- melting point
- semiconductor device
- cap
- low melting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は、低融点硝子封止型半導体装置の改良に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in low melting point glass sealed semiconductor devices.
従来の低融点硝子封止型半導体装置は、基板とキャップ
の間にリードが挿入されその三者を低融点硝子て固着し
、基板の内部空間には、半導体素子が固着され、該素子
電極とリードとを金属細線で結線されたものである。In conventional low melting point glass sealed semiconductor devices, leads are inserted between the substrate and the cap, and the three are fixed together using low melting point glass, and the semiconductor element is fixed in the internal space of the substrate, and the element electrodes and It is connected to the lead using a thin metal wire.
第１図は従来の低融点硝子封止型半導体装置の１例の断
面図、第２図は該半導体装置の内部りード周辺の部分拡
大図である。FIG. 1 is a cross-sectional view of an example of a conventional low-melting-point glass-sealed semiconductor device, and FIG. 2 is a partially enlarged view of the vicinity of an internal lead of the semiconductor device.
アルミナやステアタイト、フォルステライト等のセラミ
ックの基板または銅、コバール等の金属の基板のほぼ中
央の凹部に半導体素子２（以下チップと称す）を固着す
る為の半導体素子固着部３（以下アイランド部と称す）
となるメタライズ層７がＡｕペーストによりつくられて
いる。A semiconductor element fixing part 3 (hereinafter referred to as an island part) for fixing a semiconductor element 2 (hereinafter referred to as a chip) to a recessed portion approximately in the center of a ceramic substrate such as alumina, steatite, or forsterite or a metal substrate such as copper or Kovar. )
The metallized layer 7 is made of Au paste.
次に、鉄・ニッケル合金、銅あるいはコバール等から成
るリードフレームの放射状に配置された内部りード４は
アイランド部３の凹部周辺から基板１に重ね合わされて
各材料の熱膨脹特性に合つた低融点硝子５によつて接着
されている。又、内部リード４の先端にはアルミニウム
又は金が被着されている。この様に構成された半導体装
置用容器には、アイランド部３にチップ２を固着した後
チップ電極と内部リード４の先端との間をループ状の形
状の金属細線６で結線し、アルミナ、ステアタイト、フ
ォルステライト等のセラミックキャップ又は銅、コバー
ル等の金属キャップ８を低融点硝子５を用いて封止する
ものであつた。この様な構造の低融点硝子封止型半導体
装置において、２４ピンリード以上になつた場合にリー
ド間容量が大きくなつてしまうため内部リード４のリー
ド間隙Ｗを小さくすることができず、アイランド３の大
きさを８×７ｗｇｎ以下にすることがむずカルい。Next, the radially arranged internal leads 4 of the lead frame made of iron-nickel alloy, copper, Kovar, etc. are superimposed on the substrate 1 from around the concave part of the island part 3, and are made of a material with a low melting point that matches the thermal expansion characteristics of each material. It is bonded with glass 5. Further, the tips of the internal leads 4 are coated with aluminum or gold. In the semiconductor device container constructed in this way, after the chip 2 is fixed to the island part 3, the chip electrode and the tip of the internal lead 4 are connected with a loop-shaped thin metal wire 6, and alumina, steer, etc. A ceramic cap 8 made of tite, forsterite, etc. or a metal cap 8 made of copper, kovar, etc. was sealed using low melting point glass 5. In a low-melting-point glass-sealed semiconductor device having such a structure, when the number of leads exceeds 24 pins, the capacitance between the leads becomes large, so the lead gap W between the internal leads 4 cannot be made small, and the island 3 It is difficult to reduce the size to 8×7 wgn or less.
しかもこのアイランド径に対して非常にｊ小さなチップ
例えば１．５Ｔ！ｇｎ口程度のものを搭載した場合にチ
ップ電極と内部リードを結線する金属細線長が最大４．
７ｗｒｍにもなり、第２図に示すように金属細線６のた
るみによる金属細線同志の短絡、金属細線の引張強度の
低下、作業性の低下に７つながり、信頼性、製造歩留り
、作業性が悪くなる欠点があつた。本発明は上記欠点を
除き、大きなアイランド径の半導体装置用容器に非常に
小さなチップを搭載可能とした低融点硝子封止型半導体
装置を提供するものである。Moreover, compared to this island diameter, the chip is very small, for example 1.5T! When a device similar to a GN port is installed, the length of the thin metal wire connecting the chip electrode and internal lead is up to 4.
As shown in Fig. 2, the sagging of the thin metal wires 6 leads to short circuits between the thin metal wires, a decrease in the tensile strength of the thin metal wires, and a decrease in workability, resulting in poor reliability, manufacturing yield, and workability. There was a drawback. The present invention eliminates the above-mentioned drawbacks and provides a low-melting-point glass-sealed semiconductor device that allows a very small chip to be mounted in a semiconductor device container with a large island diameter.
本発明は、低融点硝子封止型半導体装置において、該半
導体装置の基板に固着された半導体素子電極から外部導
出リードに接続される金属細線の一部分をキャップ裏面
に設けた低融点硝子に溶融固着したことを特徴とする。The present invention relates to a low melting point glass-sealed semiconductor device, in which a portion of a thin metal wire connected to an external lead from a semiconductor element electrode fixed to a substrate of the semiconductor device is melted and fixed to a low melting point glass provided on the back surface of the cap. It is characterized by what it did.
次に、本発明を実施例により図面を用いて説明する。第
３図は本発明の半導体装置の１実施例の断面図である。Next, the present invention will be explained using examples and drawings. FIG. 3 is a sectional view of one embodiment of the semiconductor device of the present invention.
アルミナ、ステアタイト、フォルステライト等のセラミ
ック基板又は銅、コバール等の金属板１１のほぼ中央の
凹部にチップ１２を固着する為のアイランド部１３とな
るメタライズ層１７がＡｕペーストによりつくられてい
る。A metallized layer 17, which becomes an island portion 13 for fixing a chip 12 to a substantially central recess of a ceramic substrate 11 made of alumina, steatite, forsterite, etc. or a metal plate 11 made of copper, Kovar, etc., is made of Au paste.
次に、鉄・ニッケル合金、銅あるいはコバール等から成
るリードフレームの放射状に配置された内部リード１４
はアイランド部１３の凹部周辺の基板１１の周辺部１「
に重ね合わされて各材料の熱膨脹特性に合つた低融点硝
子１５によつて接着されている。又、内部リード１４の
先端にはアルミニウム又は金が被着されている。この様
に構成された半導体装置用容器には、アイランド部１３
にチップ１２を固着した後チップ電極と内部リード１４
の先端との間をループ状の形状を有して金属細線１６で
−結線する。次に、アルミナ、ステアタイト、フォルス
テライト等のセラミックキャップ又は銅、コバール等の
金属キャップ１８の中央凹部１『の深さを従来のキャッ
プの深さよりも浅くして、各種キャップ材料、リード材
料の熱膨脹係数に合つ！た低融点硝子１５を塗布する。
次に、前記キャップを使用して封止する。Next, internal leads 14 arranged radially of a lead frame made of iron-nickel alloy, copper, Kovar, etc.
is the peripheral part 1 of the substrate 11 around the concave part of the island part 13.
They are superimposed on each other and bonded together with a low melting point glass 15 that matches the thermal expansion characteristics of each material. Further, the tips of the internal leads 14 are coated with aluminum or gold. In the semiconductor device container configured in this way, the island portion 13
After fixing the chip 12 to the chip electrode and internal lead 14
A thin metal wire 16 having a loop shape is connected to the tip of the metal wire 16. Next, the depth of the central recess 1' of the ceramic cap 18 made of alumina, steatite, forsterite, etc. or the metal cap 18 made of copper, Kovar, etc. is made shallower than the depth of the conventional cap, and various cap materials and lead materials are made. Matches the coefficient of thermal expansion! A low melting point glass 15 is applied.
Next, the cap is used for sealing.
まず、第４図に示すように、前記キャップ１８を封入治
具２０の溝に入れる。次に、組立ての完了した半導体装
置用容器をキャップとずれないように３位置決めして、
その上にのせ、さらにおもり２１をのせてベルト炉等に
通して加熱し低融点硝子１５を軟化させ、半導体装置用
容器とキャップを固着封止する。これにより基板１１の
周辺部１「とキャップ１８の周辺部とがリード１４を間
にはさんで低融点硝子１５により固着１体化されて気密
封止される。この時にループ状の形状をなしている金属
細線１６の上部１６゛は、キャップ１８の中央部１『の
チップ、金属細線に相対向する面上の低融点ガラス１５
に接触して溶融固着される。すなわち低融点ガラス層の
厚さを含めて各部フ分の寸法はこのように金属細線１６
の頂上（上部）１６″が低融点硝子層１５内に入るよう
に定められている。更に内部リード１４の結線部にはシ
ール部１９すなわち周辺部の低融点硝子１５が軟化流動
して、結線部を埋込み金属細線の短絡、・はがれが防止
可能となる。以上説明したように、本発明の半導体装置
は、半導体装置用容器のアイランド径を最大のものを１
種類用意しておけば、アイランド径に対して最大のチッ
プから最小のチップまで搭載可能な構造を備えている為
に、リード間容量、金属細線のショート防止及び引張強
度を増大させ、信頼性の向上、製造原価の低減に寄与す
るものである。First, as shown in FIG. 4, the cap 18 is placed in the groove of the enclosure jig 20. Next, position the assembled semiconductor device container in three positions so that it does not shift from the cap.
A weight 21 is then placed on top of the glass, and the glass is heated through a belt furnace or the like to soften the low melting point glass 15, and the semiconductor device container and the cap are firmly sealed together. As a result, the peripheral part 1'' of the substrate 11 and the peripheral part of the cap 18 are fixed and hermetically sealed by the low melting point glass 15 with the lead 14 in between.At this time, a loop shape is formed. The upper part 16' of the thin metal wire 16 is the chip of the center part 1'' of the cap 18, and the low melting point glass 15 on the surface opposite to the thin metal wire.
It is melted and fixed when it comes into contact with. In other words, the dimensions of each part including the thickness of the low melting point glass layer are as follows:
The top (upper) 16'' of the inner lead 14 is set so that it enters the low melting point glass layer 15.Furthermore, the sealing portion 19, that is, the low melting point glass 15 at the peripheral portion softens and flows at the connection portion of the internal lead 14, thereby preventing the connection. Short-circuiting and peeling of thin metal wires can be prevented by embedding the thin metal wire.As explained above, in the semiconductor device of the present invention, the maximum island diameter of the semiconductor device container is 1.
If you prepare a variety of types, it has a structure that can mount from the largest chip to the smallest chip with respect to the island diameter, increasing the inter-lead capacitance, short-circuit prevention of thin metal wires, and tensile strength, and improving reliability. This contributes to improvement and reduction of manufacturing costs.
第１図は従来の低融点硝子封止型半導体装置の１例の断
面図、第２図は該半導体装置の内部リード周辺の部分拡
大平面図、第３図は本発明の半導体装置の１実施例の断
面図、第４図は第３図の半導体装置の製造を示す断面図
である。
１，１１・・・基板、２，１２・・・チップ（半導体素
子）、３，１３・・・チップ（半導体素子）固着部、４
，１４・・・内部リード、５，１５・・・低融点硝子、
６，１６・・・金属細線、１６″・・・ループ状の金属
細線の上部、７，１７・・・メタライズ層、８，１８・
・キャップ、９，１９・・・シール部、Ｗ・・・リード
間隙、１Ｖ・・・基板の周辺部（シール部）、１『・・
キャップの中央部、２０・・・封入治具、２１・・・お
もり。FIG. 1 is a sectional view of an example of a conventional low-melting-point glass-sealed semiconductor device, FIG. 2 is a partially enlarged plan view of the vicinity of the internal leads of the semiconductor device, and FIG. 3 is an embodiment of the semiconductor device of the present invention. An example cross-sectional view, FIG. 4, is a cross-sectional view showing the manufacture of the semiconductor device of FIG. 3. 1, 11... Substrate, 2, 12... Chip (semiconductor element), 3, 13... Chip (semiconductor element) fixing part, 4
, 14... Internal lead, 5, 15... Low melting point glass,
6,16... Metal thin wire, 16''... Upper part of loop-shaped metal thin wire, 7,17... Metallized layer, 8,18...
・Cap, 9, 19...Seal part, W...Lead gap, 1V...Periphery of board (seal part), 1'...
Center part of cap, 20... Enclosure jig, 21... Weight.
Claims (1)
ドをはさんで低融点硝子により１体化して気密封止し、
該気密封止された内部において、該基板側に固着せる半
導体素子の電極と該リードとをループ状の形状をなす金
属細線により接続された低融点硝子封止型の半導体装置
において、前記キャップの中央部であつて前記半導体素
子および前記金属細線に向い合う面には低融点硝子層が
被着しており、前記ループ状の金属細線の上部はこの低
融点硝子層内に入りこんで固着されていることを特徴と
する半導体装置。1 The periphery of the substrate and the periphery of the cap are integrated with low melting point glass with a lead sandwiched between them, and hermetically sealed.
In a low-melting-point glass-sealed semiconductor device in which the electrodes of a semiconductor element fixed to the substrate side and the leads are connected in the hermetically sealed interior by a loop-shaped thin metal wire, the cap is A low melting point glass layer is adhered to the central portion facing the semiconductor element and the thin metal wire, and the upper part of the loop-shaped thin metal wire is inserted into this low melting point glass layer and fixed. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1033478A JPS6043660B2 (en) | 1978-01-31 | 1978-01-31 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1033478A JPS6043660B2 (en) | 1978-01-31 | 1978-01-31 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54102969A JPS54102969A (en) | 1979-08-13 |
| JPS6043660B2 true JPS6043660B2 (en) | 1985-09-30 |
Family
ID=11747293
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1033478A Expired JPS6043660B2 (en) | 1978-01-31 | 1978-01-31 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6043660B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10843453B2 (en) | 2016-10-10 | 2020-11-24 | Akk Gmbh | Composite panel with barrier layer and method for manufacturing a letterpress plate |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7821129B2 (en) * | 2004-12-08 | 2010-10-26 | Agilent Technologies, Inc. | Low cost hermetic ceramic microcircuit package |
| JP2007081127A (en) * | 2005-09-14 | 2007-03-29 | Sharp Corp | Semiconductor device and method of manufacturing same |
-
1978
- 1978-01-31 JP JP1033478A patent/JPS6043660B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10843453B2 (en) | 2016-10-10 | 2020-11-24 | Akk Gmbh | Composite panel with barrier layer and method for manufacturing a letterpress plate |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54102969A (en) | 1979-08-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5389739A (en) | Electronic device packaging assembly | |
| JPH0454973B2 (en) | ||
| US5134246A (en) | Ceramic-glass integrated circuit package with integral ground and power planes | |
| JP2002110833A (en) | Semiconductor device and method of manufacturing the same | |
| JP2569400B2 (en) | Method for manufacturing resin-encapsulated semiconductor device | |
| JPS6043660B2 (en) | semiconductor equipment | |
| US3803458A (en) | Package for a microelectronic device | |
| JPH0817870A (en) | Semiconductor device | |
| JPS59111350A (en) | Semiconductor device | |
| JP3051225B2 (en) | Package for integrated circuit | |
| JPH0287655A (en) | Semiconductor device | |
| JPS59189659A (en) | Semiconductor device | |
| JP2728585B2 (en) | Package for storing semiconductor elements | |
| JPS63240055A (en) | Semiconductor device | |
| JPH0493052A (en) | Semiconductor integrated circuit device | |
| JPH05226493A (en) | Glass sealed integrated circuit | |
| JP2000150756A (en) | Resin-sealed semiconductor deive and lead frame | |
| JPH03292761A (en) | Chip carrier | |
| JP2924858B2 (en) | Lead frame and manufacturing method thereof | |
| JPS59139658A (en) | Electronic circuit device | |
| JPS61101061A (en) | Semiconductor device | |
| JPS60148151A (en) | Semiconductor device | |
| JPH0357255A (en) | Resin-sealed semiconductor device | |
| JPS59139652A (en) | Mounting structure of electronic circuit device | |
| JPH04267360A (en) | Semiconductor device |