JPS59189659A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59189659A JPS59189659A JP58065059A JP6505983A JPS59189659A JP S59189659 A JPS59189659 A JP S59189659A JP 58065059 A JP58065059 A JP 58065059A JP 6505983 A JP6505983 A JP 6505983A JP S59189659 A JPS59189659 A JP S59189659A
- Authority
- JP
- Japan
- Prior art keywords
- lead pin
- outer lead
- extended
- semiconductor device
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、ハイブリッド組立技術で用いられる半導体装
置、詳しくは同装置のパッケージ構造に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device used in hybrid assembly technology, and more particularly to a package structure for the device.
従来例の構成とその問題点
・・イブリッド組立技術で用いられる半導体装置も、高
集積化、多機能化に伴なって、アラターリ〜にピンの多
ピン化が進んでいる。従来、この種の半導体装置には、
「チップキャリア方式」と呼ばれるパッケージ法が用い
られる。第１図は、従来のテップキャリア形パッケージ
半導体装置の代表的例で、同ａは斜視図、四すはその断
面図である。この装置の詳細な構造は、第１図すに示さ
れるように、セラミック基体１０所定面上に配設された
ダイバンド部２に半導体チップ３を通常のダイボンディ
ング技術で接続し、また、半導体テップ３の各電極とリ
ード線４とは、通常のワイヤボ／
ンディング技術により、金属細線（ワイヤ）６によって
接続し、リード線４の一部をアウターリードピン６とし
て外部Ｋｍ９出し、さらに、これらを外囲樹脂体７で封
止した小型の外装体（パッケージ）である。また、アウ
ターリードピン６の構造も、第１図ａ、ｂの実線で示さ
れるように、基体下方に折り曲げて基体底面に平行させ
た、正折曲げ型１１同図すの点線で示されるように、リ
ードピンが外へ直線的に突出したー、ストレート型■お
よびリートピンを上方に折り曲げてパックージ上蓋面に
平行させた、逆折臼型■等があるが、こレラは、いずれ
も、アウターリードピン６の形状が細いもの（たとえば
、厚さ０．１６ｍｍ、幅０．４〜０．８ｍｍ程度）であ
り、製造工程中あるいは梱包、搬送中に、リードピンの
変形、切断等による損傷事故が多発していた。Conventional configurations and their problems: As semiconductor devices used in hybrid assembly technology become more highly integrated and multifunctional, the number of pins is rapidly increasing. Conventionally, this type of semiconductor device has
A packaging method called the "chip carrier method" is used. FIG. 1 shows a typical example of a conventional tip carrier type packaged semiconductor device, in which a is a perspective view and 4 is a cross-sectional view. The detailed structure of this device is as shown in FIG. Each of the electrodes 3 and the lead wire 4 are connected by a thin metal wire (wire) 6 using ordinary wire bonding technology, a part of the lead wire 4 is brought out as an outer lead pin 6, and then these are connected to the outside. It is a small exterior body (package) sealed with a resin body 7. Furthermore, the structure of the outer lead pin 6 is as shown by the solid lines in FIGS. 1a and 1b, and the normal bending die 11 is bent downwardly and parallel to the bottom surface of the base, as shown by the dotted line in the same figure. There are two types: the straight type, in which the lead pin protrudes linearly outward, and the inverted mortar type, in which the lead pin is bent upward and parallel to the upper lid surface of the package. The shape of the lead pin is thin (for example, about 0.16 mm thick and 0.4 to 0.8 mm wide), and damage accidents due to deformation or cutting of the lead pin occur frequently during the manufacturing process, packaging, and transportation. Ta.
一方、第２図の側面図のように、アウターリードピン６
′がパッケージの側面に沿って、かつ、基板底面から僅
かに突き出る程度に成形した単折曲げ型のもの、あるい
は、第３図の側面図のように、アウターリードピン６“
を基体底面側へ環状に折９曲げたものなどもあるが、こ
れらは、突出の程度が小さいだけで、リード損傷の度合
いが皆無にならないのみならず、プリント配線基板やマ
ザーボードに塔載する際の位置合せは、かえって、面倒
であり、自動実装工程での機構の複雑化を招くという問
題も生じる。On the other hand, as shown in the side view of Fig. 2, the outer lead pin 6
The outer lead pin 6" is a single-fold type that is formed along the side of the package and slightly protrudes from the bottom of the board, or as shown in the side view of Fig. 3.
There are some products that are bent into an annular shape toward the bottom of the base, but these only protrude to a small extent and do not completely eliminate the degree of lead damage. On the contrary, the alignment is troublesome, and there is also the problem of complicating the mechanism in the automatic mounting process.
発明の目的
本発明は、上述のような従来装置に見られた問題点をこ
とごとく解消し、小型、堅牢なテップキャリア形パッケ
ージ構造の半導体装置を提供するものである。OBJECTS OF THE INVENTION The present invention solves all of the problems encountered in the conventional devices as described above, and provides a small and robust semiconductor device having a tip carrier type package structure.
発明の構成
本発明は、要約するに、チップキャリア形外装体の蓋部
または基体の貼り合わせ面の一方をアウターリードピン
に沿わせて延長し、この延長面内に前記アウターリード
ピンを固持させた半導体装置であシ、これにより、アウ
ターリードピン全域がパッケージ構体の蓋部または基体
面で固定保持され、変形、析損などの事故が皆無になし
得るとともに、プリント配線基板側に同バノクージの一
面を沈め込むような抜き穴あるいは窪みを設けておけば
、アウターリードピンの露出面を同プリント配線基板な
どの配線部に接続することが答易である。Structure of the Invention To summarize, the present invention provides a semiconductor in which one of the bonding surfaces of the lid or the base of a chip carrier type exterior body is extended along outer lead pins, and the outer lead pins are fixed within this extended surface. With this device, the entire area of the outer lead pin is fixedly held on the lid or base surface of the package structure, eliminating accidents such as deformation and breakage. If a punch hole or recess is provided, the exposed surface of the outer lead pin can be easily connected to the wiring portion of the printed wiring board or the like.
実施例の説明
第４図は本発明の実施例装置であ幻、同図ａが斜視図、
同図すが断面図である。第４図すを参照して詳しく述べ
ると、セラミック板体１の上面に、焼成導体おまひ金め
っきを施して形成したグイ・ぐノド部２を設け、これに
半導体集積回路チップ３を、周知の金−シリコン共晶溶
着法により熱圧着する。この熱圧着は、窒素あるいは窒
素主体の非酸化雰囲気中、３７０℃〜４５０℃の条件下
で行なう。次に、半導体テップ３上の各電極バッド部と
リード線４とは、周知のワイヤボンディング技術によっ
て、金細線（ｉ！たはアルミニウム細線）６を用いて接
続する。次に、樹脂封止金型を用いて、上蓋部に外囲樹
脂体７を成形付着させる。このとき、外囲樹脂体７のセ
ラミック板体１との貼り合わせ面はアウターリードピン
６に沿って平坦に延長し、この延長部でアウターリード
ピン６を接着、固持する。また、この延長部はアウター
リードピン６の外先端と一致させるか、これより、わず
かに短かくして、その先端がはみ出す程度でよい。これ
により、アウターリードピン６は、基体のセラミック板
体１０側端から、外囲樹脂体７に沿って引き出される形
になる。なお、アウターリードピン６の長さは、一般的
には、０．５〜３．○古
胴程度であり、このアウターリードピン６は外弁に直線
的に延びているもの、あるいは多少折り曲げられている
ものであってもよい。DESCRIPTION OF EMBODIMENTS FIG. 4 shows an example device of the present invention; FIG.
The figure is a sectional view. To explain in detail with reference to FIG. 4, a groove part 2 formed by plating a fired conductor with gold is provided on the upper surface of the ceramic plate 1, and a semiconductor integrated circuit chip 3 is mounted on this part 2. Bonded by thermocompression using the gold-silicon eutectic welding method. This thermocompression bonding is performed at 370° C. to 450° C. in a nitrogen or non-oxidizing atmosphere mainly composed of nitrogen. Next, each electrode pad portion on the semiconductor chip 3 and the lead wire 4 are connected using a thin gold wire (i! or thin aluminum wire) 6 by a well-known wire bonding technique. Next, the outer resin body 7 is molded and attached to the upper lid portion using a resin sealing mold. At this time, the bonding surface of the outer resin body 7 to the ceramic plate body 1 extends flatly along the outer lead pin 6, and the outer lead pin 6 is bonded and fixed at this extended portion. Further, this extension portion may be made to coincide with the outer tip of the outer lead pin 6, or be made slightly shorter than this so that the tip thereof protrudes. Thereby, the outer lead pin 6 is pulled out along the outer resin body 7 from the end of the base body on the ceramic plate body 10 side. Note that the length of the outer lead pin 6 is generally 0.5 to 3. - The outer lead pin 6 may extend straight to the outer valve, or may be slightly bent.
本実施例装置をプリント配線基板あるいはマザーボード
に実装するには、その搭載部分に抜き大寸たは窪みを設
けておき、これに径小な基体部、すなわち、セラミック
板体１の部分を沈め込み、アウターリードピン６の罐出
面がプリント配線基板あるいはマザーボードの配線接続
部に当接され、通常のはんだ付は処理によって、適切な
電気接続がなされるように組み付けられる。このように
すれば、実装時の位置合せも、単に、パッケージ構体の
一部を抜き穴または窪みに、嵌め込むだけで確実に行な
われる。In order to mount the device of this embodiment on a printed wiring board or a motherboard, a large cutout or recess is provided in the mounting area, and the small diameter base portion, that is, the ceramic plate 1 is sunk into this. The protruding surface of the outer lead pin 6 is brought into contact with a wiring connection portion of a printed wiring board or a motherboard, and the assembly is performed by normal soldering so that an appropriate electrical connection can be made. In this way, positioning at the time of mounting can be performed reliably by simply fitting a part of the package structure into the punched hole or recess.
本発明装置は、基体のセラミック板体１が別の耐熱性基
体、たとえば、片面はうろう金属板（金属は銅、鉄、真
鍮などの良熱伝導体）、硬質アルマイト基板、あるいは
高温熱処理を伴なわなければ、グラスチック基体のもの
を用いることもできる。In the device of the present invention, the ceramic plate 1 as the base is made of another heat-resistant base, for example, one side is a glazed metal plate (the metal is a good heat conductor such as copper, iron, or brass), a hard alumite substrate, or a high-temperature heat-treated base. If not, a glass base material can also be used.
さらに、本発明装置は、パッケージ構体のうち基体側の
而を蓋部の貼り合わぜ面より径太に延長し、この延長面
にアウターリードピンを接着して支持した形状であって
もよい。Furthermore, the device of the present invention may have a shape in which the base side of the package structure is extended to a diameter larger than the bonding surface of the lid, and the outer lead pin is adhered to and supported by this extended surface.
発明の効果
本発明によれば、チップキャリア形外装体の蓋部または
基体の貼り合わせ面の一方をアウターリードピンに沿わ
せて延長し、この延長面内に前記アウターリードピンを
固持させたことによって、アウターリードピンの支持が
補強され、破断、切損の不良が起こらない。また、これ
により、アウターリードピンの長さも可及的に短縮でき
、小型化、高集積化に合致する半導体装置が実現される
。Effects of the Invention According to the present invention, one of the bonding surfaces of the lid portion or the base of the chip carrier type exterior body is extended along the outer lead pin, and the outer lead pin is fixed within this extended surface. The support of the outer lead pin is reinforced, and defects such as breakage and breakage do not occur. Furthermore, the length of the outer lead pin can be shortened as much as possible, thereby realizing a semiconductor device that is compatible with miniaturization and high integration.
加えて、本発明装置は、プリント配線基板あるいはマザ
ーボードの取付は位置に穴、あるいは窪みを設けておけ
ば、実装工程での位置合せが一段と容易であり、工程簡
素化を達成することにも有益である。In addition, with the device of the present invention, if a hole or depression is provided at the position where the printed wiring board or motherboard is mounted, alignment during the mounting process will be easier, which is also beneficial in achieving process simplification. It is.
第１図ａ、ｂは従来例装置の斜視図、ｂ −ｂ’断面図
、第２図、第３図は別の各従来例装置側面図、第４図ａ
、ｂは本発明実施例の斜視図、Ｂ−Ｂ’断面図である。
１・・・・・・セラミック板体、２・・・・・・ダイパ
ッド部、３・・・・・・半導体チップ、４・・・・・・
リード線、５・・・・・金属細線、６・・・・・アウタ
ーリードピン、７・・・・・・外囲樹脂体。Figures 1a and 1b are perspective views of the conventional device, b-b' sectional views, Figures 2 and 3 are side views of other conventional devices, and Figure 4a
, b are a perspective view and a BB' sectional view of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Ceramic plate body, 2... Die pad part, 3... Semiconductor chip, 4......
Lead wire, 5...Thin metal wire, 6...Outer lead pin, 7...Outer resin body.
Claims (1)
貼シ合わせ面の一方をアウターリードピンに沿わせて延
長し、この延長面内に前記アウターリードピンを固持さ
せた半導体装置。 （２ン テップキャリア形外装体の蓋部が延長面を有
する構造の特許請求の範囲第１項に記載の半導体装置。 （３） テップキャリア形外装体の蓋部がプラスチッ
ク成型体でなる特許請求の範囲第１項または第２項に記
載の半導体装置。 （４９基体がセラミック板体でなる特許請求の範囲第１
項に記載の半導体装置。[Scope of Claims] (1) A semiconductor device in which one of the lid portion of the chip carrier type exterior body or the bonding surface of the base body is extended along an outer lead pin, and the outer lead pin is fixed within this extended surface. . (2) A semiconductor device according to claim 1, in which the lid portion of the tip carrier type exterior body has an extension surface. (3) A patent claim in which the lid portion of the tip carrier type exterior body is made of a plastic molded body. The semiconductor device according to claim 1 or 2. (Claim 1 in which the substrate is a ceramic plate)
The semiconductor device described in .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58065059A JPS59189659A (en) | 1983-04-13 | 1983-04-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58065059A JPS59189659A (en) | 1983-04-13 | 1983-04-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59189659A true JPS59189659A (en) | 1984-10-27 |
Family
ID=13275996
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58065059A Pending JPS59189659A (en) | 1983-04-13 | 1983-04-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59189659A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4949131A (en) * | 1987-06-24 | 1990-08-14 | Minolta Camera Kabushiki Kaisha | Fixing apparatus |
| JPH0317644U (en) * | 1989-06-30 | 1991-02-21 | ||
| JPH03116767A (en) * | 1989-09-28 | 1991-05-17 | Nec Kyushu Ltd | Package of ic |
-
1983
- 1983-04-13 JP JP58065059A patent/JPS59189659A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4949131A (en) * | 1987-06-24 | 1990-08-14 | Minolta Camera Kabushiki Kaisha | Fixing apparatus |
| JPH0317644U (en) * | 1989-06-30 | 1991-02-21 | ||
| JPH03116767A (en) * | 1989-09-28 | 1991-05-17 | Nec Kyushu Ltd | Package of ic |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5521429A (en) | Surface-mount flat package semiconductor device | |
| US4809135A (en) | Chip carrier and method of fabrication | |
| JPH04256342A (en) | Semiconductor package | |
| US6114750A (en) | Surface mount TO-220 package and process for the manufacture thereof | |
| US7193303B2 (en) | Supporting frame for surface-mount diode package | |
| KR100226335B1 (en) | Molded plastic packaging of electronic devices | |
| US4067041A (en) | Semiconductor device package and method of making same | |
| KR0157857B1 (en) | Semiconductor package | |
| JPS59189659A (en) | Semiconductor device | |
| JPH0817870A (en) | Semiconductor device | |
| EP1018762A2 (en) | Semiconductor device and fabrication method thereof | |
| JP2690248B2 (en) | Surface mount type semiconductor device | |
| JPS6043660B2 (en) | semiconductor equipment | |
| JPS5824442Y2 (en) | semiconductor equipment | |
| JP2853695B2 (en) | Chip carrier and semiconductor integrated circuit device | |
| JPH0214558A (en) | Semiconductor integrated circuit device | |
| JP2924858B2 (en) | Lead frame and manufacturing method thereof | |
| JPS61194861A (en) | Resin sealed type semiconductor device | |
| JPS59224147A (en) | Semiconductor device | |
| JPS61101061A (en) | Semiconductor device | |
| JPS6199359A (en) | Hybrid integrated circuit device | |
| JPH08125101A (en) | Semiconductor device | |
| JPH098169A (en) | Ceramic package base body for mounting of semiconductor element | |
| JPS622626A (en) | Semiconductor device | |
| JPS59139653A (en) | Mounting method of electronic part |