JPS60148151A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60148151A JPS60148151A JP342584A JP342584A JPS60148151A JP S60148151 A JPS60148151 A JP S60148151A JP 342584 A JP342584 A JP 342584A JP 342584 A JP342584 A JP 342584A JP S60148151 A JPS60148151 A JP S60148151A
- Authority
- JP
- Japan
- Prior art keywords
- supporting substrate
- semiconductor chip
- chip
- terminals
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置、特に高密度実装を可能とする半導
体装置パッケージング技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to semiconductor devices, and particularly to semiconductor device packaging technology that enables high-density packaging.
ＩＣ，ＬＳＩのごとき半導体装置において、本体となる
半導体チップを封止する場合、従来採られている気密封
止構造は下記□のような技術である。In a semiconductor device such as an IC or an LSI, when a semiconductor chip serving as a main body is sealed, a conventionally used hermetic sealing structure is a technique as shown in □ below.
すなわちセラミックから成る容器内に半導体チップを定
着し、セラミックス番某金属の蓋で履い、ガラス層を介
して封止し、半導体チップの各電極は、セラミック容器
又はガラス層に内蔵させた配線層を通じて外部リードへ
取出□すようにしている。That is, a semiconductor chip is fixed in a container made of ceramic, covered with a lid made of a certain metal, and sealed with a glass layer, and each electrode of the semiconductor chip is connected through a wiring layer built into the ceramic container or the glass layer. I am trying to take it out to an external lead.
かかる封止構造では、半導体チップの各電極とセラミッ
ク容器内に設けた配線層の間を金ワイヤにより接続（ワ
イヤボンディング）するため、容器内部に十分な空間を
考−讐る必要があり、半導体装置全体の微細化が防ｉプ
られるという問題点があることが発明者によりあきらか
とされた。さらに又、組立封止に多くの手間がかかると
いう欠点があることも発明者によってあきらかとされた
。In such a sealing structure, each electrode of the semiconductor chip and the wiring layer provided in the ceramic container are connected using gold wires (wire bonding), so it is necessary to provide sufficient space inside the container. The inventor has found that there is a problem in that miniaturization of the entire device is prevented. Furthermore, the inventor has found that there is a drawback in that it takes a lot of time and effort to assemble and seal.
他の封止技術としては″、複数のリードを一体のフレー
ム化したリードフレーム上に半導体チップを接続し、電
極とリードの間をワイヤボンデイングした状態で樹脂成
形により封止する構造が多く採用されている。このよう
な封止構造では封止工程が簡単であるため作業性で有利
であるが、樹脂を用いるための気密性が必ずしも良くな
く、信頼性の上で問題があることが発明者によってあき
らかとされた。Other encapsulation techniques often employ a structure in which a semiconductor chip is connected to a lead frame that integrates multiple leads into an integrated frame, and the structure is encapsulated by resin molding with wire bonding between the electrodes and the leads. This type of sealing structure is advantageous in terms of workability because the sealing process is simple, but the inventors believe that the airtightness of the resin is not necessarily good and there are problems with reliability. It was made clear by.
本発明は上記した問題点を解決したものであって、その
目的とするところは、高密度実装が可能で、しかも高気
密に封止ができる半導体装置のパッケージング技術の提
供にある。The present invention solves the above-mentioned problems, and its purpose is to provide a packaging technology for semiconductor devices that allows high-density packaging and highly airtight sealing.
本発明の前記ならびにそのほかの目的と新規な特徴は本
明細書の記述、及び添付図面よりあきらかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、半導体チップの主面側を支持基板に対向させ
、この対向する面の周辺部にそって介在させた封止材に
よって封止し、さらに、チップの電極は支持基板の対向
面に設けた内部端子に接触させ、支持基板内の配線を通
じて支持基板の側面又は反対主面の外部端子に取出すよ
うにしたもので、これにより極めて実装密度を高密度化
するとともに、樹脂によらない封止であるために高気密
化することができ、前記目的を達成できる。That is, the main surface side of the semiconductor chip is placed opposite to the supporting substrate, and the semiconductor chip is sealed with a sealing material interposed along the periphery of this opposing surface, and furthermore, the electrodes of the chip are provided on the opposing surface of the supporting substrate. The terminal is brought into contact with the internal terminal and taken out through the wiring inside the support board to the external terminal on the side of the support board or on the opposite main surface.This allows for extremely high packaging density and sealing without using resin. Because of this, it is possible to achieve high airtightness and achieve the above objective.
第１図及至第４図は本発明の一実施例を示すものであっ
て、このうち第１図は組立封止された半導体装置の縦断
面図、第２図は同じく平面図である。第３図は上記半導
体装置の組立前の形態を示す正面断面斜面図である。1 to 4 show an embodiment of the present invention, in which FIG. 1 is a longitudinal sectional view of an assembled and sealed semiconductor device, and FIG. 2 is a plan view thereof. FIG. 3 is a front sectional and oblique view showing the form of the semiconductor device before assembly.
１は半導体チップであって、シリコン結晶からなる基体
１主表面にトランジスタ等の半導体素子４が形成され、
表面にアルミニウム電極５が設けられ、この電極の一部
はパッドとして銀バンプ電極６が突出する。1 is a semiconductor chip, in which a semiconductor element 4 such as a transistor is formed on the main surface of a base 1 made of silicon crystal;
An aluminum electrode 5 is provided on the surface, and a silver bump electrode 6 protrudes from a portion of this electrode as a pad.
２は支持基板であって、セラミック材を積層。2 is a support substrate on which ceramic materials are laminated.
焼結して成るものである。このセラミック基体２の内部
にはモリブデン、又はタングステン等からなるメタライ
ズ配線層７が基板の上面側と側面側とを結ぶように形成
され、上面側の配線層８は内部端子とし、側面側の配線
９を外部端子とする。It is made by sintering. Inside this ceramic base 2, a metallized wiring layer 7 made of molybdenum, tungsten, etc. is formed so as to connect the top surface side of the substrate with the side surface side.The wiring layer 8 on the top surface side serves as an internal terminal, and the wiring layer 7 on the side surface side 9 is an external terminal.
この外部端子９は第２図に示すように基板２側面に形成
した半円形のｉｌ！ １０の内面にメタライズ配線層７
を設けてなるものである。This external terminal 9 has a semicircular shape formed on the side surface of the board 2 as shown in FIG. Metalized wiring layer 7 on the inner surface of 10
It is made up of the following.
半導体チップ１と支持基板２とはその主面側を対向させ
て半導体チップ１のバンプ電極６と支持基板２の内部端
子８とを突き合せて接触させることにより接続するよう
になっている。The semiconductor chip 1 and the support substrate 2 are connected by making their principal surfaces face each other and bringing the bump electrodes 6 of the semiconductor chip 1 and the internal terminals 8 of the support substrate 2 into contact with each other.
半導体チップ１と支持基板２との対向する主面の周辺に
そって内部を取囲むように封止材１１゜１２が設けられ
ており、この封止材１１，１２によって半導体チップ１
は支持基板２に支持されるとともに気密封止される。こ
の封止材はガラス又は半田などの低融点金属からなり、
第３図に示すように、半導体チップ１の主面上及び支持
基板２の主面上にあらかじめリング状突出物１１．１２
として設けておき、両者を重ねて対向させ電極接続を行
うと同時にこの封止材を融かして封止するものである。Encapsulants 11 and 12 are provided along the periphery of the opposing main surfaces of the semiconductor chip 1 and the supporting substrate 2 so as to surround the inside thereof, and the semiconductor chip 1 is sealed by the encapsulants 11 and 12.
is supported by the support substrate 2 and hermetically sealed. This sealing material is made of glass or a low melting point metal such as solder,
As shown in FIG.
The two are stacked and facing each other to connect the electrodes, and at the same time, the sealing material is melted and sealed.
なお、上記封止材はチップと基板の一方側（例えば１２
のみ）にのみ設けておいてもよく、その場合、対向する
面にはそれと同じ材量の膜を設けておくものとする。Note that the above-mentioned sealing material is applied to one side of the chip and the substrate (for example, 12
In that case, the same amount of film shall be provided on the opposing surface.
このように組立られた半導体装置をプリント配線基板等
に実装する場合、第４図に示すように、プリント配線基
板３の配線端子１３にピン１４を植えこみ、これらピン
の側面が支持基板２の外端子の溝１０に接触させた状態
で半田ディツプすることにより実装が完了する。When mounting the semiconductor device assembled in this way on a printed wiring board or the like, as shown in FIG. Mounting is completed by soldering the external terminal in contact with the groove 10.
以上実装例で述べた本発明によれば下記のように効果が
得られる。According to the present invention described in the implementation examples above, the following effects can be obtained.
（１）半導体チップを支持基板に対向させて直接に接続
するものであるため、余分なパッケージ部分がなく、全
体として極めて小型に形成でき、高密度の実装が達成で
きる。(1) Since the semiconductor chip is directly connected to the support substrate while facing it, there is no extra package part, the overall size can be extremely small, and high-density packaging can be achieved.
（２）支持基板にセラミック積層体を使い、対向主面周
辺にそって形成したガラス又は金属による封止体を介し
て封止することにより、高気密性が得られ、高信頼性の
半導体製品を提供できる。(2) By using a ceramic laminate as a support substrate and sealing it with a glass or metal sealing body formed along the periphery of the opposing principal surface, high airtightness can be obtained, resulting in a highly reliable semiconductor product. can be provided.
（３）半導体チップ電極は対向する支持基板主面の内部
端子に接触させることによって同時に接続することがで
き、この内部端子はセラミック積層体内のメタライズ配
線を通じて支持基板側面の外部端子に接続することがで
き、ワイヤボンディング等による従来のものに比べて作
業的に簡単であり、ワイヤ切断やワイヤ接触等の事故の
おそれなく高信頼性が得られる。(3) Semiconductor chip electrodes can be connected simultaneously by contacting internal terminals on the main surfaces of the opposing support substrates, and these internal terminals can be connected to external terminals on the side surfaces of the support substrates through metallized wiring within the ceramic laminate. It is easier to work with than conventional methods using wire bonding, etc., and provides high reliability without the risk of accidents such as wire cutting or wire contact.
（４）支持基板はリードレス・タイプであるため、かさ
ばらず、プリント配線基板への高密度実装が実現できる
。(4) Since the support board is a leadless type, it is not bulky and can be mounted on a printed wiring board at high density.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが１本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically described above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor.
たとえば第５図に示すように支持基板２において外部端
子９を基板の反対主面に設けることができる。この場合
、セラミック積層体にあらかじめ縦方向の貫通孔１５を
あけておき、この貫通の内面にメタイズ配線層１６を塗
布することにより、上下主面の端子８，９間の配線によ
る接続ができる。なお、この貫通孔１５はその後半田材
等を埋めこんで半導体キップ組立の際の気密封止に耐え
る構造とする必要がある。このような支持基板２に対し
て同図に示すように半導体チップ１が支持封止された後
、プリント配線基板３の配線端子１３に対して支持基板
２の下面の外部端子９を接触させて半田ディツプにより
実装するようになる。For example, as shown in FIG. 5, external terminals 9 can be provided on the opposite main surface of the support substrate 2. In this case, a vertical through hole 15 is pre-drilled in the ceramic laminate, and a metalized wiring layer 16 is applied to the inner surface of the through hole, thereby making it possible to connect the terminals 8 and 9 on the upper and lower main surfaces by wiring. Note that this through hole 15 needs to be filled with a solder material or the like so that it has a structure that can withstand hermetic sealing during semiconductor chip assembly. After the semiconductor chip 1 is supported and sealed on such a support substrate 2 as shown in the figure, the external terminals 9 on the lower surface of the support substrate 2 are brought into contact with the wiring terminals 13 of the printed wiring board 3. It is now mounted using solder dip.
このような構造ではプリント配線基板にピンを植え込ま
なくてもよく、より簡易化、高密度化が実装できる。With such a structure, there is no need to implant pins in the printed wiring board, allowing for simpler and higher-density implementation.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である半導体装置のパッケ
ージ技術に適用した場合について説明したがそれに限定
されるものではなく、ハイブリッドＩＣのごとく基板上
に半導体装置を実装する場合にも適用できる。In the above explanation, we have mainly explained the case where the invention made by the present inventor is applied to the packaging technology of semiconductor devices, which is the background field of application, but it is not limited thereto. It can also be applied when mounting semiconductor devices.
本発明は高密度、高信頼性を要するすべての半導体装置
、例えばバイポーラＩＣ，Ｃ−ＭＯＳ ＩＣその他に適
用できるものである。The present invention is applicable to all semiconductor devices that require high density and high reliability, such as bipolar ICs, C-MOS ICs, and others.
第１図は本発明の一実施例を示し、組立てら九た半導体
装置全体の縦断面図、
第２図は同じく同平面図でそのＡ−Ａ断面が第１図に対
応する。
第３図は第１図で示した半導体装置の組立て前の形態を
示す斜面図である。
第４図は第１図で示した半導体装置をプリント配線基板
に実装する場合の形態を示す斜面図である。
第５図は本発明の他の一実施例を示す、組立てられた半
導体装置とプリント配線基板の概略断面図である。
■・・・半導体チップ、２・・・支持基板、３・・・プ
リント配線基板、４・・・半導体素子、５・・・電極、
６・・・バンプ電極、７・・・メタライズ配線、８・・
・内部端子、９・・・外部端子、ＩＯ・・・溝、１１．
１２・・・封止材、１３・・・配線端子、１４・・・ピ
ン、１５・・・貫通孔、１６・・・メタライズ配線層。FIG. 1 shows an embodiment of the present invention, and FIG. 2 is a longitudinal sectional view of the entire assembled semiconductor device, and FIG. 2 is a plan view of the same, and its AA cross section corresponds to FIG. FIG. 3 is a perspective view showing the semiconductor device shown in FIG. 1 before being assembled. FIG. 4 is a perspective view showing a configuration in which the semiconductor device shown in FIG. 1 is mounted on a printed wiring board. FIG. 5 is a schematic cross-sectional view of an assembled semiconductor device and printed wiring board, showing another embodiment of the present invention. ■... Semiconductor chip, 2... Support substrate, 3... Printed wiring board, 4... Semiconductor element, 5... Electrode,
6... Bump electrode, 7... Metallized wiring, 8...
・Internal terminal, 9...external terminal, IO...groove, 11.
12... Sealing material, 13... Wiring terminal, 14... Pin, 15... Through hole, 16... Metallized wiring layer.
Claims (1)
、上記半導体チップあ主面に対向させた支持基板とから
なり、上記半導体チップは上記対向する面の周辺部にそ
って介在させた封止材によって支持基板に支持されかつ
、気密封止されるとともに、上記半導体チップの電極は
支持基板の対向面に設けられた内部端子に接触し、支持
基板内の配線を通じて支持基板の側面又は反対側主面に
外部端子として取り出されることを特徴とする半導体装
置。 ２、上記支持基板はセラミック積層体よりなり、上記封
止材はガラス又は低融点金属よりなる特許請求の範囲第
１項に記載の半導体装置。[Scope of Claims] (1) Consisting of a semiconductor chip having a semiconductor element formed on its main surface, and a support substrate facing the main surface of the semiconductor chip, the semiconductor chip is located at the periphery of the opposing surface. The semiconductor chip is supported by the supporting substrate and hermetically sealed by the intervening sealing material, and the electrodes of the semiconductor chip are in contact with internal terminals provided on the opposite surface of the supporting substrate, and are connected through the wiring within the supporting substrate. A semiconductor device characterized in that it is taken out as an external terminal on a side surface or the opposite main surface of a support substrate. 2. The semiconductor device according to claim 1, wherein the supporting substrate is made of a ceramic laminate, and the sealing material is made of glass or a low melting point metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP342584A JPS60148151A (en) | 1984-01-13 | 1984-01-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP342584A JPS60148151A (en) | 1984-01-13 | 1984-01-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60148151A true JPS60148151A (en) | 1985-08-05 |
Family
ID=11557018
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP342584A Pending JPS60148151A (en) | 1984-01-13 | 1984-01-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60148151A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0484032A2 (en) * | 1990-10-29 | 1992-05-06 | Hewlett-Packard Company | Microchip with electrical element in sealed cavity |
| US6144090A (en) * | 1997-02-13 | 2000-11-07 | Fujitsu Limited | Ball grid array package having electrodes on peripheral side surfaces of a package board |
-
1984
- 1984-01-13 JP JP342584A patent/JPS60148151A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0484032A2 (en) * | 1990-10-29 | 1992-05-06 | Hewlett-Packard Company | Microchip with electrical element in sealed cavity |
| US6144090A (en) * | 1997-02-13 | 2000-11-07 | Fujitsu Limited | Ball grid array package having electrodes on peripheral side surfaces of a package board |
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