JPS6336686Y2 - - Google Patents
Info
- Publication number
- JPS6336686Y2 JPS6336686Y2 JP1982062579U JP6257982U JPS6336686Y2 JP S6336686 Y2 JPS6336686 Y2 JP S6336686Y2 JP 1982062579 U JP1982062579 U JP 1982062579U JP 6257982 U JP6257982 U JP 6257982U JP S6336686 Y2 JPS6336686 Y2 JP S6336686Y2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor device
- terminal
- terminal chip
- stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims 1
- 238000005513 bias potential Methods 0.000 description 10
- 239000000919 ceramic Substances 0.000 description 10
- 229910001020 Au alloy Inorganic materials 0.000 description 7
- 239000003353 gold alloy Substances 0.000 description 7
- 238000003780 insertion Methods 0.000 description 7
- 230000037431 insertion Effects 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 206010040844 Skin exfoliation Diseases 0.000 description 1
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 description 1
- DMFGNRRURHSENX-UHFFFAOYSA-N beryllium copper Chemical compound [Be].[Cu] DMFGNRRURHSENX-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Die Bonding (AREA)
Description
【考案の詳細な説明】
(a) 考案の技術分野
本考案はIC素子を搭載する気密封止形半導体
装置に係り、特に高密度集積回路を収容するIC
素子に正又は逆バイアス電位を配設するに有効な
パツケージ構造の改良に関する。[Detailed description of the invention] (a) Technical field of the invention The invention relates to a hermetically sealed semiconductor device equipped with an IC element, and particularly to an IC containing a high-density integrated circuit.
This invention relates to improvements in package structures that are effective in providing positive or reverse bias potentials to devices.
(b) 技術の背景
通常の半導体パツケージ構造として、多連リー
ドフレームに半導体素子をワイヤ方式で組込み、
トランスフアモールド成形する樹脂封止形パツケ
ージがあり、これに対し高密度集積回路を収容す
るメモリIC等の特殊メモリは信頼性及び多ピン
構成の有利性からハーメチツクシール構造のセラ
ミツクデイツプ形或は内部にリードフレームを用
い、低融点ガラスで封止するサーデイツプ形の気
密封止形パツケージが多用されている。(b) Background of the technology As a normal semiconductor package structure, semiconductor elements are assembled into a multiple lead frame using a wire method.
There are resin-sealed packages that are transfer molded, whereas special memories such as memory ICs that house high-density integrated circuits are made of ceramic dips with a hermetically sealed structure due to their reliability and advantages of multi-pin configurations. Alternatively, a hermetically sealed package in the form of a dimple is often used, which uses a lead frame inside and is sealed with low-melting glass.
一方微細加工技術の発展に伴い、IC素子が高
密度、高集積化されるに従い、各素子を形成する
不純物拡散層Ｐ，Ｎ領域が互に近接し、より多層
化されるに従い負性特性を生じ、素子特性を劣化
させる所謂寄生効果を生ずる。 On the other hand, with the development of microfabrication technology, as IC elements become denser and more highly integrated, the impurity diffusion layer P and N regions that form each element become closer to each other, and as the layers become more multilayered, negative characteristics decrease. This causes a so-called parasitic effect that deteriorates device characteristics.
このため半導体素子を正又は逆バイアス電位に
接続する回路構成を備えるのが一般的である。 For this reason, it is common to have a circuit configuration that connects the semiconductor element to a positive or reverse bias potential.
(c) 従来技術と問題点
高集積回路を収容するIC素子では、能動、受
動素子を同一半導体基板に構成する必要から、
Ｐ，Ｎ領域をなす不純物拡散層の領域分離は困難
となり益々近接する傾向にあり、寄生効果を受け
易い。(c) Conventional technology and problems In IC devices that accommodate highly integrated circuits, it is necessary to configure active and passive devices on the same semiconductor substrate.
It is difficult to separate the regions of the impurity diffusion layers forming the P and N regions, and they tend to become closer to each other, making them susceptible to parasitic effects.
IC素子面に直接バイアス印加用電極を形成で
きない高集積素子構成ではセラミツク基板を多層
化して回路形成するセラミツクデイツプ形パツケ
ージがあるがこの構造は非量産的で高価であるた
め、チツプステージ底面に直接又はターミナルチ
ツプを備えバイアス電位を接続するサーテイプ形
パツケージ構造とする。その具体例を第１図及び
第２図に示す。 For highly integrated device configurations in which bias application electrodes cannot be formed directly on the IC element surface, there is a ceramic dip-type package in which a circuit is formed by layering a ceramic substrate, but this structure is not suitable for mass production and is expensive, so A surtape type package structure with a bias potential connected directly or with a terminal chip is used. Specific examples thereof are shown in FIGS. 1 and 2.
第１図は逆バイアス電位を直接チツプステージ
を介してIC素子に印加する従来例を示すサーデ
イツプ形半導体装置を示す断面図である。 FIG. 1 is a cross-sectional view showing a conventional cer-deep type semiconductor device in which a reverse bias potential is directly applied to an IC element via a chip stage.
第２図はターミナルチツプを介してIC素子に
印加する従来例を示す断面図である。 FIG. 2 is a sectional view showing a conventional example in which a voltage is applied to an IC element via a terminal chip.
第１図においてセミラツク基板１の凹部をなす
チツプステージ２にIC素子３を金シリコン
（AuSi）合金で融着固定する。IC素子３に設けた
信号線接続用ボンデングパツドとリードフレーム
６にワイヤ５を順次ボンデング接続し、基板１と
同一材のセラミツクキヤツプ７を低融点ガラス８
で封止するサーデイツプ形半導体装置を形成す
る。基板１のチツプステージ２面に直接ワイヤ５
ａをボンデング接続し逆バイアス電位を印加す
る。この場合チツプステージ２の表面は予じめ金
薄膜が蒸着されており、IC素子３を金合金４で
融着固定に際し、導電性接着材をなす金合金４が
チツプステージ２の表面を拡散し覆うためボンデ
ングができない又は接着強度が不安定となり信頼
性に欠ける等の不都合を生ずる。 In FIG. 1, an IC element 3 is fused and fixed to a chip stage 2 forming a concave portion of a semi-rigid substrate 1 using a gold-silicon (AuSi) alloy. The wires 5 are sequentially bonded to the signal line connection bonding pads provided on the IC element 3 and the lead frame 6, and the ceramic cap 7 made of the same material as the substrate 1 is connected to the low melting point glass 8.
A deep dip type semiconductor device is formed. Connect the wire 5 directly to the 2nd surface of the chip stage of the board 1.
A is connected by bonding and a reverse bias potential is applied. In this case, a thin gold film is deposited on the surface of the chip stage 2 in advance, and when the IC element 3 is fused and fixed with the gold alloy 4, the gold alloy 4, which is a conductive adhesive, is diffused over the surface of the chip stage 2. Since the adhesive is covered, bonding cannot be performed or the adhesive strength becomes unstable, resulting in a lack of reliability.
第２図は逆バイアス電位の他の供合構成として
セラミツク基板１に設けたチツプステージ２面に
導電材のターミナルチツプ８を融着固定し、該タ
ーミナルチツプ８とリードフレーム６間にワイヤ
５a′をボンデング接続することによりバイアス電
位はターミナルチツプ８を介してIC素子３に入
力される。 FIG. 2 shows another configuration for applying a reverse bias potential, in which a terminal chip 8 made of a conductive material is fused and fixed to the surface of the chip stage 2 provided on the ceramic substrate 1, and a wire 5a' is connected between the terminal chip 8 and the lead frame 6. A bias potential is inputted to the IC element 3 via the terminal chip 8 by bonding.
ターミナルチツプ８を予じめ金薄膜層で形成さ
れたチツプステージ２面の所定位置に金合金で融
着固定し、更にIC素子３を同じく融着固定する
が加熱により先に融着したターミナルチツプ８の
接着強度に融響を与え剥離する惧れを生ずる。そ
の上狭隘個所であり作業の制約を受け信頼性を保
ちにくい。 The terminal chip 8 is fused and fixed with a gold alloy to a predetermined position on the chip stage 2 surface formed with a gold thin film layer in advance, and the IC element 3 is also fused and fixed in the same way, but the terminal chip 8 is heated and fused first. This may affect the adhesive strength of No. 8 and cause a risk of peeling. Moreover, it is a narrow space, and the work is restricted, making it difficult to maintain reliability.
第３図は第２図のセラミツク基板の上面図であ
つてチツプステージ２にそれぞれ搭載されたター
ミナルチツプ８とリード６とワイヤ５，５a′で結
合するボンデング接続を示すものである。 FIG. 3 is a top view of the ceramic substrate of FIG. 2, showing the bonding connections between the terminal chips 8 mounted on the chip stage 2, the leads 6, and the wires 5, 5a'.
（第１図及び第２図の同一符号は同一のものを
示す。）
(d) 考案の目的
本考案の目的は上記の欠点に鑑み、接着強度を
十分保持でき逆バイアス電位を印加するに有効な
半導体パツケージ構造を提供するにある。 (The same reference numerals in Figures 1 and 2 indicate the same thing.) (d) Purpose of the invention In view of the above-mentioned drawbacks, the purpose of the present invention is to maintain sufficient adhesive strength and to be effective in applying a reverse bias potential. The purpose of the present invention is to provide a semiconductor package structure.
(e) 考案の構成
サーデイツプ形半導体装置であつて、該装置の
耐熱性絶縁基板のチツプステージに円筒状のター
ミナルチツプを埋設することによつて達せられ
る。(e) Structure of the invention The present invention is a deep dip type semiconductor device, and is achieved by embedding a cylindrical terminal chip in a chip stage of a heat-resistant insulating substrate of the device.
(f) 考案の実施例
以下本考案の実施例について図面により詳述す
る。(f) Examples of the invention Examples of the invention will be described below in detail with reference to drawings.
第４図は本考案の一実施例である半導体装置を
示す断面図である。 FIG. 4 is a sectional view showing a semiconductor device which is an embodiment of the present invention.
セラミツク基板１１の凹部をなすチツプステー
ジ１２面にターミナルチツプ１３挿着用の挿入孔
１４を一体形成し、チツプステージ１２面を金蒸
着膜で被覆形成する。 An insertion hole 14 for inserting a terminal chip 13 is integrally formed on the surface of the chip stage 12 forming a concave portion of the ceramic substrate 11, and the surface of the chip stage 12 is coated with a gold vapor deposition film.
導電性に優れるベリリウム銅合金又はコーバル
合金でなる導電材を円筒形のチツプ状に形成して
ターミナルチツプ１３となし挿入孔１４に挿着し
金合金１５で融着固定させる。金合金融液はター
ミナルチツプ１３と挿入孔１４の嵌合部間隙に含
浸し、チツプステージ１２面にしつかり固定す
る。IC素子１６を所定位置に金合金１５で固定
する。従来のように個々に固着する必要はなく、
ターミナルチツプ１３は挿入孔１４に挿着され自
立するからIC素子１６を位置決めし、同時に融
着固定が可能となる。 A conductive material made of beryllium copper alloy or Kobal alloy, which has excellent conductivity, is formed into a cylindrical chip shape and is inserted into an insertion hole 14 to form a terminal chip 13, and is fused and fixed with a gold alloy 15. The gold alloy liquid is impregnated into the gap between the fitting portion of the terminal chip 13 and the insertion hole 14, and is firmly fixed to the surface of the chip stage 12. The IC element 16 is fixed in place with the gold alloy 15. There is no need to attach them individually as in the past,
Since the terminal chip 13 is inserted into the insertion hole 14 and stands on its own, it is possible to position the IC element 16 and fix it by fusion at the same time.
ワイヤボンデングは従来と同様ワイヤ１７，１
７′を図のようにIC素子１６面に設けたボンデン
グパツドとリード１８間及びターミナルチツプ１
３とリード１８′間をそれぞれボンデング接続す
る。 Wire bonding is the same as before, using wires 17 and 1.
7' between the bonding pad provided on the IC element 16 side and the lead 18 and the terminal chip 1 as shown in the figure.
3 and lead 18' are connected by bonding.
正又は逆バイアス電位はターミナルチツプ１
３、及びチツプステージ１２面を介してIC素子
１６に印加される。 Positive or reverse bias potential is terminal chip 1
3, and is applied to the IC element 16 via the chip stage 12 surface.
このようにターミナルチツプ１３を埋込むこと
により、より安定した固定構造とすることができ
る。 By embedding the terminal chip 13 in this way, a more stable fixing structure can be achieved.
第５図は他の実施例である半導体装置を示す図
である。 FIG. 5 is a diagram showing a semiconductor device according to another embodiment.
チツプステージ２２面にターミナルチツプ２３
挿着用の挿入孔２４をセラミツク基板２１の底面
まで貫通させて形成したもので、半導体装置の底
面より半導体特性の一部が測定監視できる利点が
ある。 Terminal chip 23 on chip stage 22
The insertion hole 24 for insertion is formed to penetrate to the bottom surface of the ceramic substrate 21, which has the advantage that part of the semiconductor characteristics can be measured and monitored from the bottom surface of the semiconductor device.
(g) 考案の効果
以上詳細に説明したように本考案のバイアス印
加用のターミナルチツプを埋込構造とすることに
より、従来に比して接着強度は向上し特性の安定
化が期待できる優れた効果がある。(g) Effects of the device As explained in detail above, the terminal chip for bias application of the present invention has an embedded structure, which improves the adhesive strength and stabilizes the characteristics compared to the conventional method. effective.
第１図、第２図は従来例の逆バイアス電位接続
構成をもつ半導体装置を示す断面図。第３図はセ
ラミツク基板のワイヤボンデング構成を示す上面
図、第４図は本考案の一実施例である半導体装置
を示す断面図、第５図は本考案の他の実施例を示
す半導体装置の断面図である。図中１１，２１は
セラミツク基板、１２，２２はチツプステージ、
１３，２３はターミナルチツプ、１４，２４は挿
入孔、１５は金合金、１６は半導体素子、１７，
１７′はワイヤ、１８，１８′はリードを示す。
1 and 2 are cross-sectional views showing a semiconductor device having a conventional reverse bias potential connection configuration. FIG. 3 is a top view showing a wire bonding structure of a ceramic substrate, FIG. 4 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention, and FIG. 5 is a semiconductor device showing another embodiment of the present invention. FIG. In the figure, 11 and 21 are ceramic substrates, 12 and 22 are chip stages,
13 and 23 are terminal chips, 14 and 24 are insertion holes, 15 is a gold alloy, 16 is a semiconductor element, 17,
17' is a wire, and 18 and 18' are leads.
Claims (1)
中央凹部に設けたチツプステージにIC素子を装
着し、該基板と同一材又は金属キヤツプでハーメ
チツクシールする気密封止形半導体装置であつ
て、該チツプステージに円筒状のターミナルチツ
プを埋設し、且つ導電性材料で該IC素子とター
ミナルチツプとを電気的に結合してなることを特
徴とする半導体装置。 A hermetically sealed semiconductor device in which lead terminals are arranged on the outside, an IC element is mounted on a chip stage provided in the central recess of a heat-resistant insulating substrate, and hermetically sealed with the same material as the substrate or a metal cap. A semiconductor device comprising: a cylindrical terminal chip embedded in the chip stage; and the IC element and the terminal chip are electrically coupled using a conductive material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982062579U JPS58164240U (en) | 1982-04-28 | 1982-04-28 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982062579U JPS58164240U (en) | 1982-04-28 | 1982-04-28 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58164240U JPS58164240U (en) | 1983-11-01 |
| JPS6336686Y2 true JPS6336686Y2 (en) | 1988-09-28 |
Family
ID=30072727
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1982062579U Granted JPS58164240U (en) | 1982-04-28 | 1982-04-28 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58164240U (en) |
-
1982
- 1982-04-28 JP JP1982062579U patent/JPS58164240U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58164240U (en) | 1983-11-01 |
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