JPH0287655A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0287655A JPH0287655A JP24148088A JP24148088A JPH0287655A JP H0287655 A JPH0287655 A JP H0287655A JP 24148088 A JP24148088 A JP 24148088A JP 24148088 A JP24148088 A JP 24148088A JP H0287655 A JPH0287655 A JP H0287655A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- cap
- heat sink
- bonded
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 238000007789 sealing Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 abstract description 13
- 239000002184 metal Substances 0.000 abstract description 13
- 229910052782 aluminium Inorganic materials 0.000 abstract description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 6
- 238000003466 welding Methods 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 239000000853 adhesive Substances 0.000 description 10
- 230000001070 adhesive effect Effects 0.000 description 10
- 239000000463 material Substances 0.000 description 8
- 238000005219 brazing Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 229910000833 kovar Inorganic materials 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 239000010959 steel Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920003217 poly(methylsilsesquioxane) Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000013464 silicone adhesive Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に、ヒートシンクを搭載
した半導体装置構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device structure equipped with a heat sink.
従来、ヒートシンク搭載型半導体装置は、第３図に示す
ように、半導体素子４は所謂フェイス・ダウン方式で搭
載され、ヒートシンク２は半導体素子搭載用金属板１０
上に接着剤８を介して設けられるのが通常である。従っ
て、外部端子３は半導体素子４の気密封止用キャップ６
の周辺に配列される。この場合、ヒートシンク２の搭載
方法には金属ロウ材や樹脂系接着剤を用いる方法または
ネジ止め等で機械的に接続するなどの手段が用いられる
。金属ロウ材を用いる場合は、第３図に示すように半導
体素子搭載面に金属板１０を用い、その金属板裏面に、
ヒートシンクを接着することが多い。この金属板１０に
は、放熱効果を重視する場合は銅、タングステンを用い
、また、コスＩ・を重視する場合はモリブデンやコバー
ルが用いられる。ヒートシンクの素材には、アルミニウ
ム銅が多く用いられ、アルミニウム製のヒートシンクを
金属ロウ材で接着する場合は、ヒートシンクの接合部に
鋼材等が用いられている。Conventionally, in a heat sink mounting type semiconductor device, as shown in FIG.
It is usually provided on top with an adhesive 8 interposed therebetween. Therefore, the external terminal 3 is connected to the hermetic sealing cap 6 of the semiconductor element 4.
are arranged around. In this case, the heat sink 2 may be mounted using a method using a metal brazing material or a resin adhesive, or a mechanical connection using screws or the like. When using a metal brazing material, as shown in FIG. 3, a metal plate 10 is used on the semiconductor element mounting surface, and the back side of the metal plate is
Heat sinks are often glued. For this metal plate 10, copper or tungsten is used when the heat dissipation effect is important, and molybdenum or Kovar is used when the cost I is important. Aluminum and copper are often used as materials for heat sinks, and when aluminum heat sinks are bonded with a metal brazing material, steel or the like is used for the joints of the heat sinks.
樹脂系の接着材を用いる場合は、金属ロウ材を用いる場
合のように半導体素子搭載面に金属板を用いる必要も、
また、アルミニウム製ヒートシンクの接合部に鋼材等を
用いる必要もなく構造が簡単になる。この場合の接着材
には、一般にエポキシ系或いはシリコーン系のものが用
いられている。When using a resin-based adhesive, it is also necessary to use a metal plate on the semiconductor element mounting surface, as is the case when using metal brazing material.
Furthermore, there is no need to use steel or the like for the joints of the aluminum heat sink, and the structure becomes simpler. The adhesive used in this case is generally an epoxy or silicone adhesive.
このように、上述した従来のし−１−シンク搭載型半導
体装置は、半導体素子がフェイス・ダウン方式で搭載さ
れ半導体素子搭載面と同一方向に外部端子が設けられて
いるので、半導体素子が外部端子に囲まれた構造となる
。そのため、半導体素子搭載面と反対方向に外部端子を
設ける場合、すなわち、半導体素子をフェイス・アップ
方式で搭載する場合に比べて搭載できる半導体素子の大
きさに制限が加わる９特に、最近は実装密度向上のため
半導体装置の小型化が強く要求されるようになり、ピン
・グリッド型半導体装置の出現を見るに至っているので
半導体素子の大きさに制限を受けるフェイス・タウン構
造の不利は免かれない。In this way, in the conventional one-sink mounting type semiconductor device described above, the semiconductor element is mounted face-down and the external terminals are provided in the same direction as the semiconductor element mounting surface, so that the semiconductor element is not exposed to the outside. It has a structure surrounded by terminals. Therefore, when external terminals are provided in the opposite direction to the semiconductor element mounting surface, in other words, the size of the semiconductor element that can be mounted is limited compared to when the semiconductor element is mounted face-up. There has been a strong demand for miniaturization of semiconductor devices to improve performance, and we have seen the emergence of pin-grid type semiconductor devices, so the disadvantages of the face-town structure, which is limited by the size of the semiconductor element, cannot be avoided. .
本発明の目的は、上記の状況に鑑み、多数ピン構造の高
集積度半導体素子を搭載し得るヒートシンク搭載型半導
体装置を提供することである。SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a heat sink mounted semiconductor device capable of mounting a highly integrated semiconductor element having a multi-pin structure.
本発明によれば、半導体装置は、電気絶縁基板と、前記
絶縁基板の凹部底面にフェース・アップ方式でマウント
される半導体素子と、前記半導体素子のフェースと反対
側の絶縁基板面から引出される複数個の外部端子と、前
記半導体素子を気密封止する気密封止用キャップと、前
記気密封止用キャップを含んで構成される。According to the present invention, a semiconductor device includes an electrically insulating substrate, a semiconductor element mounted face-up on the bottom surface of a recess of the insulating substrate, and a semiconductor device that is pulled out from a surface of the insulating substrate opposite to the face of the semiconductor element. The device includes a plurality of external terminals, an airtight sealing cap that hermetically seals the semiconductor element, and the airtight sealing cap.
すなわち、本発明によれば、半導体素子は電気絶縁基板
上にフェイス・アップ方式で搭載され素子サイズ上の制
限が取払われると共に、ヒートシンクは半導体素子搭載
面と同方向に搭載され、半導体素子の気密封止用キャッ
プの周辺部、または、キャップ上面を含む広い面積上に
接着されることとなるので、十分な放熱効果を得ること
かできる。That is, according to the present invention, the semiconductor element is mounted face-up on an electrically insulating substrate, eliminating restrictions on the element size, and the heat sink is mounted in the same direction as the semiconductor element mounting surface, so that the semiconductor element can be mounted face-up. Since it is bonded over a wide area including the periphery of the airtight sealing cap or the top surface of the cap, a sufficient heat dissipation effect can be obtained.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示す半導体装置の断面図で
ある。本実施例によれば、電気絶縁基板１には一般に多
く使われるアルミナ・セラミック材が用いられ、また、
半導体素子４には外形が約４３ｍｍＸ４３ｍ＋ｎ、外部
端子３の総数２０８本のピン・グリッド・アレイ形素子
が搭載される。この際、気密封止は金属製のシール・リ
ング７と金属製のキャップ６とを抵抗溶接により接着す
るシーム・ウェルド法で行われる。シール・リング７に
はコバールにニッケルめっきまたは金めつきを施し、ま
た、キャップ６にはニッケル・クラッド・コバール材を
用いる。一般にシーム・ウェルド法によると、キャップ
６の板厚が厚い場合接着が難かしくなり、比較的弱い外
力で変形する可能性がある。従って、本実施例ではヒー
トシンク２を接着したときの圧力でキャップ６が変形し
、ボンデインク・ワイヤー５と電気的短絡をおこす可能
性を避けるため、ヒートシンク２側に凹部が設けられる
。ヒートシンク２にはアルミニウムが用いられ表面はア
ルマイト加工される。また、放熱面積を広げるためその
表面には放熱フィンが設けられる。接着材８には、市販
の熱硬化性エポキシ樹脂が用いられる。この際、接着剤
８はヒートシンク２のアルミニウム材、電気絶縁基板１
−のアルミナ・セラミック材に比べて熱抵抗か高いので
、極力薄くする必要がある。本実施例では加熱硬化時に
加圧することにより接着剤８の厚みを約５０〜１００μ
ｍとした。FIG. 1 is a sectional view of a semiconductor device showing one embodiment of the present invention. According to this embodiment, the electrically insulating substrate 1 is made of a commonly used alumina ceramic material, and
The semiconductor element 4 is equipped with a pin grid array element having an outer diameter of approximately 43 mm x 43 m+n and a total of 208 external terminals 3. At this time, hermetic sealing is performed by a seam welding method in which the metal seal ring 7 and the metal cap 6 are bonded together by resistance welding. The seal ring 7 is made of Kovar with nickel plating or gold plating, and the cap 6 is made of nickel-clad Kovar material. Generally, according to the seam-weld method, if the cap 6 is thick, it becomes difficult to bond the cap 6, and there is a possibility that the cap 6 may be deformed by a relatively weak external force. Therefore, in this embodiment, a recess is provided on the heat sink 2 side in order to avoid the possibility that the cap 6 will be deformed by the pressure when the heat sink 2 is bonded and cause an electrical short circuit with the bonding wire 5. The heat sink 2 is made of aluminum, and its surface is alumite processed. Further, in order to increase the heat radiation area, heat radiation fins are provided on the surface. For the adhesive 8, a commercially available thermosetting epoxy resin is used. At this time, the adhesive 8 is applied to the aluminum material of the heat sink 2 and the electrically insulating substrate 1.
-It has a higher thermal resistance than the alumina/ceramic material, so it needs to be made as thin as possible. In this embodiment, the thickness of the adhesive 8 is reduced to approximately 50 to 100 μm by applying pressure during heat curing.
It was set as m.
第２図は本発明の他の実施例を示す半導体装置の断面図
である。本実施例は、金属ロー材、フリッパガラス樹脂
系接着材等から成る接着剤９を用いて気密封止した場合
を示す。また、キャップ６は電気絶縁基板１内に落し込
まれた構造となっており、ヒートシンク２との接着面が
平坦化される。この構造にすると、キャップ６の厚みを
厚くでき、十分な強度を持たせられるので、ヒートシン
ク２をキャップ６上にも延在するように接着することが
できる。FIG. 2 is a sectional view of a semiconductor device showing another embodiment of the present invention. This embodiment shows a case in which hermetic sealing is performed using an adhesive 9 made of a metal brazing material, a flipper glass resin adhesive, or the like. Further, the cap 6 has a structure in which it is sunk into the electrically insulating substrate 1, and the surface to be bonded to the heat sink 2 is flattened. With this structure, the cap 6 can be made thicker and have sufficient strength, so that the heat sink 2 can be bonded so as to extend over the cap 6 as well.
以上詳細に説明したように、本発明を実施することによ
って得られる効果は、サイズの大きな半導体素子を搭載
したヒートシンク搭載型半導体装置が得られることであ
り、例えば、外部端子２０８本のピン・グリッド・アレ
イ型半導体装置に実施した場合は、従来に比べ約２．５
倍の面積比をもつ半導体素子の搭載を可能としたことで
ある。As explained in detail above, the effect obtained by carrying out the present invention is that a heat sink mounted semiconductor device equipped with a large-sized semiconductor element can be obtained, for example, a pin grid with 208 external terminals.・When applied to array type semiconductor devices, it is approximately 2.5 times lower than conventional
This made it possible to mount semiconductor elements with double the area ratio.
第１図は本発明の一実施例を示す半導体装置の断面図、
第２図は本発明の他の実施例を示す半導体装置の断面図
、第３図は従来のヒートシンク搭載型半導体装置の断面
図である。
１・・・電気絶縁基板、２・・・ヒートシンク、３・・
・外部端子、４・・・半導体素子、５・・・ボンデイン
ク・ワイヤー、６・・・気密封止用キャップ、７・・・
シールリング、８，９・・・接着剤。FIG. 1 is a cross-sectional view of a semiconductor device showing an embodiment of the present invention;
FIG. 2 is a sectional view of a semiconductor device showing another embodiment of the present invention, and FIG. 3 is a sectional view of a conventional heat sink mounted type semiconductor device. 1... Electrical insulation board, 2... Heat sink, 3...
- External terminal, 4... Semiconductor element, 5... Bonde ink wire, 6... Hermetic sealing cap, 7...
Seal ring, 8, 9...adhesive.
Claims (1)
アップ方式でマウントされる半導体素子と、前記半導体
素子のフェースと反対側の絶縁基板面から引出される複
数個の外部端子と、前記半導体素子を気密封止する気密
封止用キャップと、前記気密封止用キャップを含む電気
絶縁基板全面に接着されるヒートシンクとを含むことを
特徴とする半導体装置。An electrically insulating substrate and a face plate on the bottom of the recess of the insulating substrate.
A semiconductor element mounted in a top-up manner, a plurality of external terminals drawn out from the insulating substrate surface opposite to the face of the semiconductor element, an airtight sealing cap for hermetically sealing the semiconductor element, and the airtight sealing cap for airtightly sealing the semiconductor element. 1. A semiconductor device comprising: a heat sink adhered to the entire surface of an electrically insulating substrate including a sealing cap.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24148088A JPH0287655A (en) | 1988-09-26 | 1988-09-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24148088A JPH0287655A (en) | 1988-09-26 | 1988-09-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0287655A true JPH0287655A (en) | 1990-03-28 |
Family
ID=17074940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24148088A Pending JPH0287655A (en) | 1988-09-26 | 1988-09-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0287655A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH047175U (en) * | 1990-05-09 | 1992-01-22 | ||
| JPH0722657A (en) * | 1993-06-30 | 1995-01-24 | Nippon Buroaa Kk | Thermo module |
| EP0797253A2 (en) * | 1996-03-19 | 1997-09-24 | Matsushita Electric Industrial Co., Ltd | Chip carrier and semiconductor device using the same |
| KR100479913B1 (en) * | 1997-09-10 | 2005-06-16 | 삼성테크윈 주식회사 | Pga package |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS593554B2 (en) * | 1977-04-27 | 1984-01-24 | サンリツ工業株式会社 | Outer blade for electric razor and its manufacturing method |
-
1988
- 1988-09-26 JP JP24148088A patent/JPH0287655A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS593554B2 (en) * | 1977-04-27 | 1984-01-24 | サンリツ工業株式会社 | Outer blade for electric razor and its manufacturing method |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH047175U (en) * | 1990-05-09 | 1992-01-22 | ||
| JPH0722657A (en) * | 1993-06-30 | 1995-01-24 | Nippon Buroaa Kk | Thermo module |
| EP0797253A2 (en) * | 1996-03-19 | 1997-09-24 | Matsushita Electric Industrial Co., Ltd | Chip carrier and semiconductor device using the same |
| EP0797253A3 (en) * | 1996-03-19 | 1999-04-14 | Matsushita Electric Industrial Co., Ltd | Chip carrier and semiconductor device using the same |
| KR100479913B1 (en) * | 1997-09-10 | 2005-06-16 | 삼성테크윈 주식회사 | Pga package |
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