JPS5891646A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5891646A JPS5891646A JP18843881A JP18843881A JPS5891646A JP S5891646 A JPS5891646 A JP S5891646A JP 18843881 A JP18843881 A JP 18843881A JP 18843881 A JP18843881 A JP 18843881A JP S5891646 A JPS5891646 A JP S5891646A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- mounting
- semiconductor chip
- chip
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Abstract
Description
【発明の詳細な説明】 発明の技術分野 フリーツブチップ型の半導体装置の改良構造に関する。[Detailed description of the invention] Technical field of invention This invention relates to an improved structure of a free-chip type semiconductor device.
発明の技術的背景
半導体装置でＩ Ｃ−？Ｌ ８ Ｉのチップをセラミッ
クパッケージまたはリードフレームに取着はワイヤボン
ディングを施している構造のものが多い臥この構造はボ
ンディングワイヤが例えば２５ミグロン ３０ 、％ク
ロンのような細径で次項に述べる問題点がある。次にフ
リップチップ構造は第１図に示すように、セラミック、
ガラスエポキシ樹脂等の電気絶縁基板（１）の上面に銅
の配線パターン（２）がめつき、ラミネート被着され、
これのバンプベッド部（２ｍ）、 （２ｂ）・・・に半
導体チップ（３）が電極を導出するはんだバンプ（３ａ
）、 （３ｂ）・・・で接続され電気的接続と取着とが
達成されていたが次項にのべる間醜点がある。なお、（
４）は前記配線パターン上の電気絶縁層である。Technical Background of the Invention In a semiconductor device, IC-? In many cases, the L8I chip is attached to a ceramic package or lead frame using wire bonding.This structure has problems as described in the next section because the bonding wire has a small diameter of, for example, 25 microns or 30%. There is a point. Next, the flip-chip structure is as shown in Figure 1.
A copper wiring pattern (2) is plated and laminated on the top surface of an electrically insulating substrate (1) made of glass epoxy resin, etc.
The semiconductor chip (3) has solder bumps (3a) from which electrodes are led out to the bump bed portions (2m), (2b)...
), (3b)..., and electrical connection and attachment were achieved, but there are disadvantages that will be discussed in the next section. In addition,(
4) is an electrical insulating layer on the wiring pattern.
背景技術の問題点
畝上のワイヤボンディング方式によるものはボンディン
グワイヤの強度が低く断線や、変形による短絡等を生じ
やすい。次に７リツプチツプ構造は接続部の疲労強度を
高くする必要が１り９、強制冷却の手段を要し、チップ
の裏面にビンを接触させて放熱をはかるなどを必要とす
る。Problems with the Background Art In the method of wire bonding on ridges, the bonding wire has low strength and is prone to breakage and short circuits due to deformation. Next, the 7-lip chip structure requires high fatigue strength at the connecting portions19, requires means for forced cooling, and requires measures such as bringing a bottle into contact with the back surface of the chip to dissipate heat.
発明の目的
スリップチップ型半導体装置の半導体チップが外囲器に
強固に取着される構造および堆着部が電極導出のバンプ
部を気密に封止する構造を提供する。OBJECTS OF THE INVENTION It is to provide a structure in which a semiconductor chip of a slip chip type semiconductor device is firmly attached to an envelope, and a structure in which a deposited portion hermetically seals a bump portion from which an electrode is led out.
発明の概ｇ！（構成と作用）
フリップチップ型半導体装置において、半導体チップを
外囲器に取着するために半導体チップに電気的接続をし
ない取着用はんだ部を、また外囲器に前記取着用はんだ
部に対応させて取着ベッド部を夫々設けて取着を施す構
造と堆着部が電極導出のバンプ部を取囲み気密封止をな
す構造である。Overview of the invention! (Structure and operation) In a flip chip type semiconductor device, in order to attach a semiconductor chip to an envelope, a mounting solder part that does not make an electrical connection to the semiconductor chip is provided, and the envelope corresponds to the mounting solder part. There is a structure in which attachment bed portions are provided and attachment is performed, and a structure in which the deposition portion surrounds the bump portion for leading out the electrode to form an airtight seal.
発明の実施例
（発明の第１実施例は第２図および第３図に示すように
従来の半導体チップ（３）の電極を導出するはんだバン
プ（３ａ）、 （３ｂ）・・・はそのｉまで、これらを
取巻、〈取着用はんだ部（５）が設けられている。この
取着用はんだ部は半導体チップとは電気的に接続されて
いない。次に電気絶縁基板（１）に配線パターン（２）
が形成されこの配線Ｊターンは半導体チップのはんだバ
ンプ部（３ｍ）、 （３ｂ）・・・に対応するバンプベ
ッド部（２ｍ）、 （２ｂ）・・・を有し、前記半導体
チップの取着用はんだ部（５）に対応する取着ばラド部
（６）が電気絶縁層（４）を介して前記配線パターン上
に積層して形成されている。そして半導体チップ（３）
ｔｉその取着用はんだ部（５）を電気絶縁基板（りの
取着ベッド部（６）Ｋはんだ接合することによって強固
な取着が達成される。この取着手段によシ、はんだバン
プ部Ｋｔｉ応力が荷重されないので破損をうけることな
く、また配線パターンが剥離されることもない、なお、
この取着けんだ（ベッド）部の形状は図示のような短貴
状でも、またはその細円形等任意の形状に選んでよい。Embodiment of the Invention (The first embodiment of the invention is as shown in FIGS. 2 and 3, where the solder bumps (3a), (3b), etc. for leading out the electrodes of the conventional semiconductor chip (3) are A solder part (5) for mounting is provided surrounding these. This solder part for mounting is not electrically connected to the semiconductor chip. Next, a wiring pattern is formed on the electrically insulating board (1). (2)
is formed, and this wiring J-turn has bump bed portions (2m), (2b)...corresponding to the solder bump portions (3m), (3b)... of the semiconductor chip, and is used for mounting the semiconductor chip. A mounting pad portion (6) corresponding to the solder portion (5) is formed by laminating on the wiring pattern with an electrical insulating layer (4) interposed therebetween. And semiconductor chip (3)
A strong attachment is achieved by soldering the solder portion (5) for attachment to the attachment bed portion (6) of the electrically insulating substrate. Since no stress is applied, there will be no damage, and the wiring pattern will not peel off.
The shape of this attached (bed) portion may be any shape, such as a short crown as shown in the figure, or a thin circular shape.
発明の第２実施例は第４図および第５図に示すように従
来の半纏体チップ（３）の電極を導出するはんだバンプ
（３ｍ）、 （３ｂ）・・・はそのままで、これらを取
巻く取着用はんだ部（５つが設けられている。この取着
用はんだ部は半導体チップとは電気的に接続されていな
い。次に電気絶縁基板（１）に配線パターン（２）が形
成されこの配線パターンは半導体チップのはんだバンプ
部（３ａ）、 （３ｂ）・・・に対応するバンプ（ラド
部（２ａ）、 （２ｂ）・・・を有するが、これらバン
プにラド部を取巻き前記半導体チップの取着用はんだ部
（５）Ｋ対応する取着ベッド部（６）が電気絶縁層（４
）を介して前記配線パターン上に積層して形成されてい
る。そして半導体チップ（３）はその取着用はんだ部（
５つを電気絶縁基板（１）の取着ベッド部（６）にはん
だ接合することＫよって強固な取着が達成される。この
取着手段により、はんだバンプ部には応力が荷重されな
いので破損をうけることなく、また配線パターンが剥離
されることもない、さらにこの実施例によると電極導出
の配線接続部がシールされるので半導体チップに対し湿
気、汚染等を防躾でき、品質保証面からも有効である。In the second embodiment of the invention, as shown in FIGS. 4 and 5, the solder bumps (3 m), (3b), etc. that lead out the electrodes of the conventional semi-integrated chip (3) are left as they are, and the solder bumps (3b) surrounding these are left as they are. Solder parts for mounting (5 are provided. These solder parts for mounting are not electrically connected to the semiconductor chip. Next, a wiring pattern (2) is formed on the electrically insulating board (1), and this wiring pattern has bumps (rad parts (2a), (2b), etc.) corresponding to the solder bump parts (3a), (3b), etc. of the semiconductor chip, but these bumps surround the solder bump parts (2a), (2b), etc. of the semiconductor chip. The mounting solder part (5) K has a corresponding mounting bed part (6) that is
) is laminated and formed on the wiring pattern via the wiring pattern. The semiconductor chip (3) is attached to the solder part (
A strong attachment is achieved by soldering the five pieces to the attachment bed portion (6) of the electrically insulating substrate (1). With this attachment means, no stress is applied to the solder bump portion, so it will not be damaged, and the wiring pattern will not be peeled off.Furthermore, according to this embodiment, the wiring connection portion of the electrode lead-out is sealed. It can protect semiconductor chips from moisture, pollution, etc., and is also effective in terms of quality assurance.
まえ、半導体チップの放熱も向上される効果もある。First, it also has the effect of improving heat dissipation of the semiconductor chip.
発明の第３の実施例は第６図に半導体チップ（３）の下
面を示す（電気絶縁基板面については図示を省略する）
ように、はんだバンプ部（３ａ）、 （３ｂ）・・・に
よって囲まれる内側に取着用はんだ部（５＃）が設けら
れている。図示は省略されるが畝上の第１の実施例にお
けると同様に、電気絶縁基板の配線パターン上に前記取
着用はんだ部（５“）Ｋ対応する取着ベッド部が設けら
れ、これとはんだ接合が達成され強固に取着される。そ
して半導体チップの放熱にも有効である。The third embodiment of the invention is shown in FIG. 6, which shows the bottom surface of the semiconductor chip (3) (the electrically insulating substrate surface is not shown).
As shown, a solder portion (5#) for attachment is provided inside surrounded by the solder bump portions (3a), (3b), . . . . Although illustration is omitted, as in the first embodiment on the ridge, a mounting bed portion corresponding to the solder portion (5") K for mounting is provided on the wiring pattern of the electrically insulating board, and this Bonding is achieved and firmly attached, and it is also effective in dissipating heat from semiconductor chips.
発明の第４の実施例は第７図に半導体チップ（３）の下
面を示すように、はんだバンプ部（３ａ）、 （ａｂ）
・・・を取囲む取着用はんだ部（５つ（発明の第２の実
施例に示し九本のと同じ）と、前記はんだ７７７部に取
囲まれた取着用はんだ部（５′）（発明の第３の実施例
に示したものと同じ）とを兼備し、強固な取着とこれに
よる電極の導出接続が保饅される。In the fourth embodiment of the invention, as shown in FIG. 7, the lower surface of the semiconductor chip (3) has solder bump portions (3a), (ab).
. . . surrounding the solder portions (5 (same as the nine shown in the second embodiment of the invention)), and the solder portion (5') for attachment surrounded by the solder 777 portion (the present invention). (same as that shown in the third embodiment), and strong attachment and lead-out connection of the electrodes thereby are maintained.
また、半導体チップの放熱も良好になる。Furthermore, heat dissipation from the semiconductor chip is also improved.
発明の効果
半導体チップの外囲器への取着強度が顕著に向上し、電
極の導出接続が保躾され完全になる。また、半導体チッ
プの放熱も向上する。さらに、堆層ベッド部によるシー
ルド効果を期待することもできる。Effects of the Invention: The strength of the attachment of the semiconductor chip to the envelope is significantly improved, and the lead-out connections of the electrodes are maintained and perfected. Furthermore, heat dissipation from the semiconductor chip is also improved. Furthermore, it is also possible to expect a shielding effect from the stacked bed portion.
第１図は従来の半導体装置の一部の断面図、第２図およ
び第３図は第１実施例の半導体装置の一部を示す第２図
は第３図のＡ Ａ’縁に沿う断面図、第４図は第２の実
施例の半導体チップを示す下面図、第５図は配線パター
ンを示す図、第６図は第３の実施例の半導体チップの下
面図、第７図は第４の実施例の半導体チップの下面図で
ある。
１ ｍ気絶縁基板
２ 配線パターン
２ａ、２ｂ・・・ バンプベッド部３ 半
導体チップ
３ａ、３ｂ・・・ （電極を導出する）はんだバン
プ５ 、５’、 ５“ 半導体チップの取着用はん
だ部６ 電気絶縁基板の散着ベッド部イ
ｊ
代理人 弁理士 井 上 −男
第 １ 図
第 ３ 図
第 ５ 図
第６図
４″
第 ７ 図FIG. 1 is a cross-sectional view of a part of a conventional semiconductor device, and FIGS. 2 and 3 are a cross-sectional view of a part of the semiconductor device of the first embodiment. 4 is a bottom view of the semiconductor chip of the second embodiment, FIG. 5 is a diagram showing the wiring pattern, FIG. 6 is a bottom view of the semiconductor chip of the third embodiment, and FIG. 7 is a bottom view of the semiconductor chip of the third embodiment. FIG. 4 is a bottom view of the semiconductor chip of Example 4; 1 meter insulation board 2 Wiring patterns 2a, 2b... Bump bed section 3 Semiconductor chips 3a, 3b... Solder bumps 5, 5', 5'' (for leading out electrodes) Solder section 6 for attaching semiconductor chips Electrical Insulating substrate scattering bed section Ij Agent Patent attorney Mr. Inoue Figure 1 Figure 3 Figure 5 Figure 6 Figure 4'' Figure 7
Claims (2)
半導体チップにその電極を導出するはんだバンプ部とこ
のチップを外囲器に取着けるだめの取着用はんだ部、お
よび外囲器に前記チップのはんだ、Ｓ７７部と取着用は
んだ部とに夫々対応して設けられたバンプベッド部と取
着ベッド部とを具備したことを特徴とする半導体装置。(1) In a semiconductor device with a flip-chip structure,
A solder bump part for leading out the electrodes to the semiconductor chip, a solder part for attaching the chip to the envelope, and a solder part for attaching the chip to the envelope correspond to the S77 part and the solder part for attaching, respectively. A semiconductor device comprising a bump bed section and a mounting bed section.
区域を取囲み形成されて半導体チップのはんだバンプ部
品缶封止するように外囲器に対応して設けられた取着ベ
ッド部に取着し友ことを特徴とする特許請求の範囲第１
項記載の半導体装置。(2) A mounting bed portion is provided corresponding to the envelope so that the solder portion for mounting is formed surrounding a part of the main surface of the semiconductor chip and seals the solder bump component can of the semiconductor chip. Claim 1 characterized in that it is an attached friend.
1. Semiconductor device described in Section 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18843881A JPS5891646A (en) | 1981-11-26 | 1981-11-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18843881A JPS5891646A (en) | 1981-11-26 | 1981-11-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5891646A true JPS5891646A (en) | 1983-05-31 |
Family
ID=16223674
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18843881A Pending JPS5891646A (en) | 1981-11-26 | 1981-11-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5891646A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62144346A (en) * | 1985-12-19 | 1987-06-27 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit element |
| JPS62202532A (en) * | 1986-03-03 | 1987-09-07 | Agency Of Ind Science & Technol | Semiconductor device |
| JPH02244648A (en) * | 1989-03-16 | 1990-09-28 | Nippon Avionics Co Ltd | Mounting of electronic component, and surface mounting type electronic component and mounting substrate used therefor |
| US6724084B1 (en) | 1999-02-08 | 2004-04-20 | Rohm Co., Ltd. | Semiconductor chip and production thereof, and semiconductor device having semiconductor chip bonded to solid device |
| FR2949903A1 (en) * | 2009-09-07 | 2011-03-11 | Soc Fr Detecteurs Infrarouges Sofradir | Electronic component e.g. infrared radiation detector, hybridization method, involves forming fusible cords for defining cleaning liquid flow channel in connection zone, consecutive to fusion of cords |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51147255A (en) * | 1975-06-13 | 1976-12-17 | Hitachi Ltd | Semiconductor device |
| JPS5290268A (en) * | 1976-01-23 | 1977-07-29 | Hitachi Ltd | Semiconductor device |
| JPS5348469A (en) * | 1976-10-14 | 1978-05-01 | Mitsubishi Electric Corp | Production of hybrid integrated circuit device |
-
1981
- 1981-11-26 JP JP18843881A patent/JPS5891646A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51147255A (en) * | 1975-06-13 | 1976-12-17 | Hitachi Ltd | Semiconductor device |
| JPS5290268A (en) * | 1976-01-23 | 1977-07-29 | Hitachi Ltd | Semiconductor device |
| JPS5348469A (en) * | 1976-10-14 | 1978-05-01 | Mitsubishi Electric Corp | Production of hybrid integrated circuit device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62144346A (en) * | 1985-12-19 | 1987-06-27 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit element |
| JPS62202532A (en) * | 1986-03-03 | 1987-09-07 | Agency Of Ind Science & Technol | Semiconductor device |
| JPH02244648A (en) * | 1989-03-16 | 1990-09-28 | Nippon Avionics Co Ltd | Mounting of electronic component, and surface mounting type electronic component and mounting substrate used therefor |
| US6724084B1 (en) | 1999-02-08 | 2004-04-20 | Rohm Co., Ltd. | Semiconductor chip and production thereof, and semiconductor device having semiconductor chip bonded to solid device |
| US7045900B2 (en) | 1999-02-08 | 2006-05-16 | Rohm Co., Ltd | Semiconductor chip and production thereof, and semiconductor device having semiconductor chip bonded to solid device |
| FR2949903A1 (en) * | 2009-09-07 | 2011-03-11 | Soc Fr Detecteurs Infrarouges Sofradir | Electronic component e.g. infrared radiation detector, hybridization method, involves forming fusible cords for defining cleaning liquid flow channel in connection zone, consecutive to fusion of cords |
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