JPS62144346A - Semiconductor integrated circuit element - Google Patents
Semiconductor integrated circuit elementInfo
- Publication number
- JPS62144346A JPS62144346A JP60286084A JP28608485A JPS62144346A JP S62144346 A JPS62144346 A JP S62144346A JP 60286084 A JP60286084 A JP 60286084A JP 28608485 A JP28608485 A JP 28608485A JP S62144346 A JPS62144346 A JP S62144346A
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- Prior art keywords
- chip
- solder
- electrode
- layer
- onto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2901—Shape
- H01L2224/29012—Shape in top view
- H01L2224/29013—Shape in top view being rectangular or square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体集積回路素子に７′）ｊするもので、牛
〒にｔ’ｐ部接続用電、１夕パノト上に突起型１曳を形
成し、その突起電極を接続すべき回路基板の電極上に直
接接合する半導体装法（以下フリップ、チップ法と呼ぶ
）に使用される半導体集積回路素子の放熱構造に特徴を
有するものである。[Detailed Description of the Invention] Industrial Field of Application The present invention is applied to semiconductor integrated circuit devices, in which a t'p connection voltage is provided on the cowl, and a protrusion type 1 is formed on the panoto. However, it is characterized by a heat dissipation structure of a semiconductor integrated circuit element used in a semiconductor mounting method (hereinafter referred to as a flip or chip method) in which the protruding electrode is directly bonded to an electrode of a circuit board to which it is connected.
従来の技術
近年の電子機器の小型、軽量化は、めざましいものがあ
り、その中でも半導体集積回路素子（以下ＩＣと呼ぶ）
の発達が非常な速さで開発され前記目的のため大きく寄
与している。従来のＩＣはＤｌＬ型、ＳＩＬ型、フラッ
トパッケージ型等プラスチックパッケージ型が主流であ
った。しかし、最近はＩＣのプラスチックパッケージ品
自体のサイズが太きすぎるという状況になり、ＩＣの高
密度・実装方法が１つの大きな課題となってきた。Conventional technology The size and weight reduction of electronic devices in recent years has been remarkable, and among them, semiconductor integrated circuit elements (hereinafter referred to as ICs) have become smaller and lighter.
The development of technology has been developed at a very rapid pace and has contributed significantly to the above-mentioned purpose. Conventional ICs have mainly been of plastic package type, such as DIL type, SIL type, and flat package type. However, recently, the size of IC plastic packages themselves has become too thick, and the high density and mounting methods of ICs have become a major issue.
その解決策としＣ１フリップチップ法が産業機器、特に
コンピュータ関係に広く使用され“Ｃいる。すなわち、
第４図に示した如く、表面に電極１７を形成した配線基
板１６に、ＩＣチップ１８の表面に一端が露出するよう
に形成された突起電極（以下バンブと呼ぶ）１９を直接
接合する構造が王に使用されている。なお、第４図にお
い・Ｃ１１５は導体１７の保護用コーティング層、２０
は外部結線用アルミパッド、２１は内部回路、２２は前
記外部結線用アルミパッド２０とバンプ１９の異種材料
を接合するだめの下地電極であり通常２〜３種の金属を
使用している。２３は内部回路保護用ガラス、２４は外
部絶縁層である。As a solution, the C1 flip-chip method is widely used in industrial equipment, especially computers.
As shown in FIG. 4, there is a structure in which a protruding electrode (hereinafter referred to as a bump) 19 formed with one end exposed on the surface of an IC chip 18 is directly bonded to a wiring board 16 on which an electrode 17 is formed. used by the king. In addition, in FIG. 4, C115 is a protective coating layer for the conductor 17, and 20
2 is an aluminum pad for external connection, 21 is an internal circuit, and 22 is a base electrode for bonding the different materials of the aluminum pad 20 for external connection and bump 19, and usually two or three types of metals are used. 23 is a glass for protecting the internal circuit, and 24 is an external insulating layer.
発明が解決しようとする問題点
ＩＣチップ中の集積度は指数函数的な速度で高密度にな
り、チップ自体のサイズも大きくなってきＣいる。その
ため、ｒＣチップ自体の消費電力も増大し、その結果、
チップの温度上昇が無視出来なくなりつつある。コンピ
ュータ等の工Ｃチップを多数実装した基板等は水冷、空
冷等の方法で強制的に冷却しているのが現状である。先
に説明したフリノブチップ実装においても、従来の方式
は突起電極を通じて熱を放散するのが主体であるだめ高
消費電力のチップの実装が困難であったり複雑な放熱方
式をとらざるをえなかった。本発明は単純な構造、方法
で効率よく、放熱するフリップチップを提供する事にあ
る。Problems to be Solved by the Invention The degree of integration in IC chips is increasing at an exponential rate, and the size of the chips themselves is also increasing. Therefore, the power consumption of the rC chip itself increases, and as a result,
The rise in chip temperature is becoming impossible to ignore. Currently, circuit boards for computers and the like on which a large number of C chips are mounted are forcibly cooled by methods such as water cooling and air cooling. Even in the above-mentioned fly-knob chip mounting, the conventional method mainly dissipates heat through protruding electrodes, making it difficult to mount chips with high power consumption or requiring complicated heat dissipation methods. The object of the present invention is to provide a flip chip that efficiently dissipates heat with a simple structure and method.
問題点を解決するだめの手段
上記問題を解決するため本発明の半導体集積回路素子は
、ＩＣチップ表面の突起電極以外の表面部に熱の良導体
で放熱極を形成し、この部分をフＩＪ 、ｙブチノブ実
装する外回路基板部に接続あるいは接触させ、その部分
を通じて大部分の放熱を行なわんとするものである。Means for Solving the Problems In order to solve the above problems, the semiconductor integrated circuit device of the present invention forms a heat dissipation pole with a good heat conductor on the surface area of the IC chip surface other than the protruding electrodes, and this area is covered with an IJ, It is intended to be connected or in contact with the external circuit board portion on which the y-butchinob is mounted, and to dissipate most of the heat through that portion.
作用
上述の構造のフリップチップは、従来の突起電極部だけ
よりの放熱に加えて、突起電極部以外の部分に形成され
た放熱極からも熱が放熱され、その部分の面積は、一般
に突起電極部より数十倍以」二の大きさに設定可能であ
り、非常に優れた放熱効果が期待できるものである。Function In the flip chip with the above structure, in addition to the conventional heat dissipation from only the protruding electrode part, heat is also radiated from the heat dissipating electrode formed in the part other than the protruding electrode part, and the area of that part is generally smaller than the protruding electrode part. It can be set to a size that is several tens of times larger than that of the previous one, and an extremely excellent heat dissipation effect can be expected.
実施例
以下本発明の実施例について図面を参照しながら説明す
る。第１図および第２図は本発明の半導体集積回路チッ
プの一実施例の断面図および斜視図であり、第３図は同
チップの実装状態を示す断面図である。EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings. 1 and 2 are a cross-sectional view and a perspective view of an embodiment of a semiconductor integrated circuit chip of the present invention, and FIG. 3 is a cross-sectional view showing a state in which the chip is mounted.
第１図、第２図および第３図において、第４図の従来例
と同様な構成部品には同一符号を付しており、本実施例
の従来構成と異なる点は、外部絶縁層２４上の一部に放
熱用の導体層２５とその上に接続用のバンプ２６が形成
されている点である。In FIGS. 1, 2, and 3, the same reference numerals are given to the same components as in the conventional example shown in FIG. A conductor layer 25 for heat dissipation and bumps 26 for connection are formed on a part of the conductor layer 25.
以下本実施例のＩＣチップの構造、作り方について詳細
に述べる。通常の工程により、アルミパッド２０、内部
回路２１、および保護用ガラス層２３が形成されたＩＣ
ウェハー全面に、絶縁層２４となる。例えば、感光性ポ
リイミド樹脂をスピナー法、ディップ法等で例えば１μ
厚みで塗布し、その上に外部結線用パッド２Ｑに対応す
る位置にそのパッド２０と同じ大きさか、少し大きめの
パターンを形成したマスクを乗せ、紫外線露光、エツチ
ングし、前記パッド部分２０に対応する位置の前記のポ
リイミド樹脂層を除去する。次に、通常使用されている
メタル層例えば、クロム、銅を全面に蒸着法あるいは、
スパッタリング法等で付ける。次にウェハー全面にホト
レジストをスピナー法等で塗布し、外部結線用パッド部
２２および放熱用の導電体層２５の形成部を残すように
フォトマスクを乗せ露光、エツチングすることにより、
バンド２０と導電体層２５の形成される孔を形成する。The structure and manufacturing method of the IC chip of this example will be described in detail below. An IC on which an aluminum pad 20, an internal circuit 21, and a protective glass layer 23 are formed by a normal process.
An insulating layer 24 is formed over the entire surface of the wafer. For example, photosensitive polyimide resin is processed using spinner method, dipping method, etc.
A mask with a pattern the same size or slightly larger than the pad 20 is placed on top of it at a position corresponding to the external connection pad 2Q, exposed to ultraviolet rays, and etched to form a pattern corresponding to the pad portion 20. The polyimide resin layer at the position is removed. Next, a commonly used metal layer such as chromium or copper is deposited on the entire surface, or
Attach by sputtering method etc. Next, a photoresist is applied to the entire surface of the wafer using a spinner method or the like, and a photomask is placed on the wafer so as to leave the external connection pad portion 22 and the heat dissipation conductor layer 25 formed by exposing and etching.
A hole is formed in which the band 20 and the conductor layer 25 are to be formed.
次に下地の全面鋼部を陰極に銅をさきにホトエッチした
孔の開いた部分にのみ、電気メブキしＣ銅を厚く付ける
。厚みは、例えば、１ｄ〜２０μとする。そして、不要
となったホトレジスト層、全面につけた銅、クロム層を
エツチングして除去する。次に外部結線用パッド部２０
と導′π体層２５の表面に、例えば、スクリーン印刷法
でハンダクリームを印刷して乗せ、最後にそのハンダ組
成で決まる融点以上に加熱しハンダを融かし同一高さの
バンプ部１９と２６を形成する。第２図は第１図の斜視
図を示したものである。本実施例のバンプ１９と２６の
材料はハンタ゛を使用したが、通常使用されている金等
も適用できる事は勿論のことである。なお、前記クロム
、銅蒸着層はアルミパソｌ’ ２０強固に接続すると共
に上部メタルがアルミハツト２０中に拡散するのを防止
するためのものであり、銅メッキ層は、ハンダ付けする
だめに必要なものである。勿論、別のバンプ材になれば
、前記２２の材料は変える必要がある。Next, use the entire steel part of the base as a cathode, and apply a thick layer of C copper to only the areas where the holes that were photo-etched are electromeshed. The thickness is, for example, 1d to 20μ. Then, the unnecessary photoresist layer and the copper and chromium layers deposited on the entire surface are removed by etching. Next, the external connection pad section 20
For example, solder cream is printed and placed on the surface of the conductor layer 25 using a screen printing method, and finally the solder is heated to a temperature higher than the melting point determined by the solder composition to melt the solder and form bumps 19 of the same height. Form 26. FIG. 2 shows a perspective view of FIG. 1. Hunter is used as the material for the bumps 19 and 26 in this embodiment, but it goes without saying that commonly used materials such as gold can also be used. The chromium and copper vapor deposited layers are used to firmly connect the aluminum solder plate 20 and to prevent the upper metal from diffusing into the aluminum hat 20, and the copper plating layer is necessary for soldering. It is. Of course, if a different bump material is used, the material 22 needs to be changed.
次に本発明のバンプ付ＩＣチップの実装形態について第
３図を用いて説明する。ＩＣチップを実装する基板（例
えば樹脂系、セラミック系、金属系等）１６の表面に本
発明のＩＣチップ上のバンプ１９，２６と相対するパタ
ーンの電極１７を形成し、そのパターン上にノ・ンダク
リームを薄く塗布し、その上に先に示しだ本発明のバン
プ付ＩＣチップを乗せ加熱、ハンダ融触して接続する。Next, a mounting form of the bumped IC chip of the present invention will be explained using FIG. 3. An electrode 17 having a pattern facing the bumps 19 and 26 on the IC chip of the present invention is formed on the surface of a substrate 16 (for example, resin-based, ceramic-based, metal-based, etc.) on which an IC chip is mounted, and no. A thin layer of solder cream is applied, and the bumped IC chip of the present invention shown above is placed on top of the solder cream, and the IC chip with bumps of the present invention is heated and connected by solder melting.
放熱用バンプ２６に相対するパターン１γはアースライ
ンに接続しても、あるいは、独立していても良いが、ア
ースラインに接続する方が安定する。The pattern 1γ facing the heat dissipation bump 26 may be connected to the ground line or may be independent, but it is more stable if it is connected to the ground line.
まだ、先の本発明のＸＯチップ形成時に放熱用バンプを
ＩＣチップのアースラインに直接接続しておけば、ＩＣ
チップの回路がそれ以外の回路より受ける干渉等の影響
を少なくすることができ、大きな効果を発揮する。なお
、実施例ではハンダバンプの接続法の１例を示したが、
金バンプ等を本発明に適用する場合は、熱、・１４音波
併用ギヤングボンテイング去を使用する必要がある。However, if the heat dissipation bump is directly connected to the ground line of the IC chip when forming the XO chip of the present invention, the IC
It is possible to reduce the effects of interference on the chip's circuits from other circuits, which is highly effective. In addition, although one example of the connection method of solder bumps was shown in the example,
When applying gold bumps or the like to the present invention, it is necessary to use a combination of heat and 14-sound wave bonding.
さらに、実施例の説明中絶縁層をポリイミド樹脂につい
て示したが、他の樹脂系絶縁体やガラス系等無機系の絶
縁体を使用してもなんら障害なく使用出来る。Further, although the insulating layer is made of polyimide resin in the description of the embodiments, other resin-based insulators or inorganic insulators such as glass-based insulators may be used without any problem.
発明の効果
以上実施例で説明したように本発明の半導体集積回路素
子は、工Ｃチップの表面より直接外回路基板に熱の良導
体をかいして放熱するため、非常に放熱性が良く、従来
法では使用出来なかった消費電力の大きいＩＣチップも
簡単に使用できる。Effects of the Invention As explained in the embodiments, the semiconductor integrated circuit device of the present invention radiates heat from the surface of the engineered C chip directly to the external circuit board through a good conductor of heat, so it has very good heat dissipation properties and is superior to the conventional one. IC chips with high power consumption, which could not be used under the law, can be easily used.
また、放熱用バンプをアースラインに接続すれば、工Ｃ
チップ上の回路が電気的に１呆獲され干渉、妨害等の影
響を下げることができる。Also, if you connect the heat dissipation bump to the ground line, you can
Since the circuits on the chip are electrically isolated, the effects of interference, interference, etc. can be reduced.
第１図は本発明のＩＣ回路素子の一実施例を示す断面図
、第２図はその斜視図、第３図は同実施例のＩＣ回路素
子を列回路基板に接合した状態を示す断面図、第４図は
従来のＩＣ回路素子の列回路基板への接合状態を示す断
面図である。
１５・・・・・・列回路基板上導体の保護コートｅ、１
６・・・・・列回路基板、１７・・・・・・外回路基板
上の導体、１８・・・・工Ｃチップ、１９・・・・・・
バンプ、２０・・・・・アルミパッド、２１・・・・・
・工Ｃ中の回路、２２・・・・・アルミパッドとパンダ
材との接合用層、２３・・・・ＩＣ中の回路保護層、２
４・・・・・・外部絶縁層、２５・・・・・放熱極接続
用下地金属層、２６・・・・・・放熱険バンプ。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名１８
−ｒｃ ＋：、７’
２４−一一りＬ印！−７！（舎７噛
２６− 朕ｎ尿＼・叡。FIG. 1 is a cross-sectional view showing an embodiment of the IC circuit element of the present invention, FIG. 2 is a perspective view thereof, and FIG. 3 is a cross-sectional view showing the IC circuit element of the same embodiment bonded to a column circuit board. , FIG. 4 is a cross-sectional view showing a conventional IC circuit element bonded to a column circuit board. 15... Protective coat e, 1 for conductor on column circuit board
6...Column circuit board, 17...Conductor on outer circuit board, 18...C chip, 19...
Bump, 20... Aluminum pad, 21...
・Circuit in construction C, 22... bonding layer between aluminum pad and panda material, 23... circuit protection layer in IC, 2
4... External insulating layer, 25... Base metal layer for connecting heat dissipation electrode, 26... Heat dissipation bump. Name of agent: Patent attorney Toshio Nakao and 1 other person18
-rc +:, 7' 24-11 L mark! -7! (Sha 7 bite 26- My urine＼・叡.
Claims (3)
けられた絶縁層を貫通して外部に露出した外部回路接続
用の突起電極と、前記絶縁層上に配置され前記突起電極
より大なる表面積を有する熱良導体よりなる放熱極を有
する半導体集積回路素子。(1) A protruding electrode for external circuit connection, one end of which is connected to the internal circuit and the other end of which is exposed to the outside by penetrating an insulating layer provided on the external surface, and a protruding electrode arranged on the insulating layer and connected to the protruding electrode. A semiconductor integrated circuit element having a heat dissipation pole made of a good thermal conductor with a large surface area.
ることを特徴とする特許請求の範囲第１項記載の半導体
集積回路素子。(2) The semiconductor integrated circuit device according to claim 1, wherein the heat dissipation electrode is made of the same material as the protruding electrode.
ていることを特徴とする特許請求の範囲第１項記載の半
導体集積回路素子。(3) The semiconductor integrated circuit device according to claim 1, wherein the heat dissipation pole is electrically connected to a ground wire of the internal circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60286084A JPS62144346A (en) | 1985-12-19 | 1985-12-19 | Semiconductor integrated circuit element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60286084A JPS62144346A (en) | 1985-12-19 | 1985-12-19 | Semiconductor integrated circuit element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62144346A true JPS62144346A (en) | 1987-06-27 |
Family
ID=17699731
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60286084A Pending JPS62144346A (en) | 1985-12-19 | 1985-12-19 | Semiconductor integrated circuit element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62144346A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05315507A (en) * | 1992-05-12 | 1993-11-26 | Nec Corp | Semiconductor integrated circuit chip and semiconductor device |
| WO1999019907A1 (en) * | 1997-10-14 | 1999-04-22 | Amkor Technology, Inc. | Method and construction for thermally enhancing a microelectronic package |
| EP0942635A1 (en) * | 1998-03-10 | 1999-09-15 | STMicroelectronics S.r.l. | A power semiconductor device for "flip-chip" connections |
| KR100248682B1 (en) * | 1995-04-27 | 2000-03-15 | 가네꼬 히사시 | Semiconductor device and installing method of semiconductor chip |
| WO2002095817A2 (en) * | 2001-05-21 | 2002-11-28 | Infineon Technologies Ag | Semiconductor component with at least one semiconductor chip on a base chip serving as substrate and method for production thereof |
| JP2003224158A (en) * | 2002-01-25 | 2003-08-08 | Texas Instruments Inc | Flip chip for substrate assembly with no bump and polymer layer |
| EP1316998A3 (en) * | 2001-11-06 | 2005-02-02 | Texas Instruments Incorporated | Bumpless Chip Scale Device (CSP) and board assembly |
| WO2010038345A1 (en) * | 2008-10-03 | 2010-04-08 | パナソニック株式会社 | Wiring board, semiconductor device and method for manufacturing the same |
| US7910471B2 (en) | 2004-02-02 | 2011-03-22 | Texas Instruments Incorporated | Bumpless wafer scale device and board assembly |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5591134A (en) * | 1978-12-28 | 1980-07-10 | Mitsubishi Electric Corp | Semiconductor device |
| JPS5891646A (en) * | 1981-11-26 | 1983-05-31 | Toshiba Corp | Semiconductor device |
-
1985
- 1985-12-19 JP JP60286084A patent/JPS62144346A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5591134A (en) * | 1978-12-28 | 1980-07-10 | Mitsubishi Electric Corp | Semiconductor device |
| JPS5891646A (en) * | 1981-11-26 | 1983-05-31 | Toshiba Corp | Semiconductor device |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05315507A (en) * | 1992-05-12 | 1993-11-26 | Nec Corp | Semiconductor integrated circuit chip and semiconductor device |
| KR100248682B1 (en) * | 1995-04-27 | 2000-03-15 | 가네꼬 히사시 | Semiconductor device and installing method of semiconductor chip |
| WO1999019907A1 (en) * | 1997-10-14 | 1999-04-22 | Amkor Technology, Inc. | Method and construction for thermally enhancing a microelectronic package |
| US6028354A (en) * | 1997-10-14 | 2000-02-22 | Amkor Technology, Inc. | Microelectronic device package having a heat sink structure for increasing the thermal conductivity of the package |
| US6423576B1 (en) | 1997-10-14 | 2002-07-23 | Amkor Technology, Inc. | Microelectronic device package having a heat sink structure for increasing the thermal conductivity of the package |
| EP0942635A1 (en) * | 1998-03-10 | 1999-09-15 | STMicroelectronics S.r.l. | A power semiconductor device for "flip-chip" connections |
| US6291893B1 (en) | 1998-03-10 | 2001-09-18 | Stmicroelectronics S.R.L. | Power semiconductor device for “flip-chip” connections |
| WO2002095817A3 (en) * | 2001-05-21 | 2003-06-19 | Infineon Technologies Ag | Semiconductor component with at least one semiconductor chip on a base chip serving as substrate and method for production thereof |
| WO2002095817A2 (en) * | 2001-05-21 | 2002-11-28 | Infineon Technologies Ag | Semiconductor component with at least one semiconductor chip on a base chip serving as substrate and method for production thereof |
| EP1316998A3 (en) * | 2001-11-06 | 2005-02-02 | Texas Instruments Incorporated | Bumpless Chip Scale Device (CSP) and board assembly |
| JP2003224158A (en) * | 2002-01-25 | 2003-08-08 | Texas Instruments Inc | Flip chip for substrate assembly with no bump and polymer layer |
| EP1333494A3 (en) * | 2002-01-25 | 2006-06-07 | Texas Instruments Incorporated | Semiconductor device and method of fabricating a semiconductor assembly |
| JP4698125B2 (en) * | 2002-01-25 | 2011-06-08 | テキサス インスツルメンツ インコーポレイテッド | Flip chip for substrate assembly without bumps and polymer layers |
| US7910471B2 (en) | 2004-02-02 | 2011-03-22 | Texas Instruments Incorporated | Bumpless wafer scale device and board assembly |
| WO2010038345A1 (en) * | 2008-10-03 | 2010-04-08 | パナソニック株式会社 | Wiring board, semiconductor device and method for manufacturing the same |
| US8283775B2 (en) | 2008-10-03 | 2012-10-09 | Panasonic Corporation | Wiring board, semiconductor device and method for manufacturing the same |
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