WO2002095817A3 - Semiconductor component with at least one semiconductor chip on a base chip serving as substrate and method for production thereof - Google Patents

Semiconductor component with at least one semiconductor chip on a base chip serving as substrate and method for production thereof Download PDF

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Publication number
WO2002095817A3
WO2002095817A3 PCT/DE2002/001783 DE0201783W WO02095817A3 WO 2002095817 A3 WO2002095817 A3 WO 2002095817A3 DE 0201783 W DE0201783 W DE 0201783W WO 02095817 A3 WO02095817 A3 WO 02095817A3
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WO
WIPO (PCT)
Prior art keywords
chip
semiconductor
base
semiconductor chip
substrate
Prior art date
Application number
PCT/DE2002/001783
Other languages
German (de)
French (fr)
Other versions
WO2002095817A2 (en
Inventor
Holger Huebner
Original Assignee
Infineon Technologies Ag
Holger Huebner
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Holger Huebner filed Critical Infineon Technologies Ag
Publication of WO2002095817A2 publication Critical patent/WO2002095817A2/en
Publication of WO2002095817A3 publication Critical patent/WO2002095817A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01—ELECTRIC ELEMENTS
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
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    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/8182—Diffusion bonding
    • H01L2224/8183—Solid-solid interdiffusion
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
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    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Thermistors And Varistors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

According to the invention, a semiconductor component, with at least one semiconductor chip (20) on a base chip (10) serving as substrate has contact surfaces (11, 21) made of metal on the at least one semiconductor chip (20) and the base chip (10). The semiconductor chip (20) and the base chip (10) are thus arranged relative to each other such that the corresponding contact surfaces of the at least one semiconductor chip (20) and the base chip (10) are facing each other and the facing contact surfaces (11, 21) are electrically connected to each other. The separation between a contact surface of the at least one semiconductor chip (20) and the corresponding contact surface of the base chip (10) is less than 10 µm. The base chip (10) comprises components produced by a first technique, whilst the at least one semiconductor chip (20) comprises components produced by means of a second technique.
PCT/DE2002/001783 2001-05-21 2002-05-17 Semiconductor component with at least one semiconductor chip on a base chip serving as substrate and method for production thereof WO2002095817A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10124774.5 2001-05-21
DE10124774.5A DE10124774B4 (en) 2001-05-21 2001-05-21 Semiconductor component having at least one semiconductor chip on a base chip serving as substrate and method for its production

Publications (2)

Publication Number Publication Date
WO2002095817A2 WO2002095817A2 (en) 2002-11-28
WO2002095817A3 true WO2002095817A3 (en) 2003-06-19

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2002/001783 WO2002095817A2 (en) 2001-05-21 2002-05-17 Semiconductor component with at least one semiconductor chip on a base chip serving as substrate and method for production thereof

Country Status (4)

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CN (1) CN100461356C (en)
DE (1) DE10124774B4 (en)
TW (1) TW544903B (en)
WO (1) WO2002095817A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10219353B4 (en) * 2002-04-30 2007-06-21 Infineon Technologies Ag Semiconductor device with two semiconductor chips
DE10300711B4 (en) 2003-01-10 2007-10-04 Infineon Technologies Ag Method for passivating a semiconductor chip stack
DE10303588B3 (en) * 2003-01-29 2004-08-26 Infineon Technologies Ag Vertical assembly process for semiconductor devices
DE10313047B3 (en) 2003-03-24 2004-08-12 Infineon Technologies Ag Semiconductor chip stack manufacturing method incorporates bridging of conductor paths of one semiconductor chip for design modification
EP1617473A1 (en) * 2004-07-13 2006-01-18 Koninklijke Philips Electronics N.V. Electronic device comprising an ESD device
DE102004055677A1 (en) * 2004-11-18 2006-06-01 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Compound chip carrier, as an image sensor for military night sights and the like, has a chip bonded to the substrate with contact surfaces and conductive zones through the substrate

Citations (5)

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DE2902002A1 (en) * 1979-01-19 1980-07-31 Gerhard Krause Three=dimensional integrated circuits - mfd. by joining wafer stack with contacts through conductive adhesive
JPS62144346A (en) * 1985-12-19 1987-06-27 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit element
US5790384A (en) * 1997-06-26 1998-08-04 International Business Machines Corporation Bare die multiple dies for direct attach
JP2000294724A (en) * 1999-04-09 2000-10-20 Matsushita Electronics Industry Corp Semiconductor device and its manufacture
US6204089B1 (en) * 1999-05-14 2001-03-20 Industrial Technology Research Institute Method for forming flip chip package utilizing cone shaped bumps

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US5422435A (en) * 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5977640A (en) * 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
US5897341A (en) * 1998-07-02 1999-04-27 Fujitsu Limited Diffusion bonded interconnect
US6392304B1 (en) * 1998-11-12 2002-05-21 United Memories, Inc. Multi-chip memory apparatus and associated method
DE19907276C2 (en) * 1999-02-20 2001-12-06 Bosch Gmbh Robert Method for producing a solder connection between an electrical component and a carrier substrate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2902002A1 (en) * 1979-01-19 1980-07-31 Gerhard Krause Three=dimensional integrated circuits - mfd. by joining wafer stack with contacts through conductive adhesive
JPS62144346A (en) * 1985-12-19 1987-06-27 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit element
US5790384A (en) * 1997-06-26 1998-08-04 International Business Machines Corporation Bare die multiple dies for direct attach
JP2000294724A (en) * 1999-04-09 2000-10-20 Matsushita Electronics Industry Corp Semiconductor device and its manufacture
US6204089B1 (en) * 1999-05-14 2001-03-20 Industrial Technology Research Institute Method for forming flip chip package utilizing cone shaped bumps

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 011, no. 376 (E - 563) 8 December 1987 (1987-12-08) *
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 13 5 February 2001 (2001-02-05) *
TORNITA Y ET AL: "Copper bump bonding with electroless metal cap on 3 dimensional stacked structure", XP010534483 *

Also Published As

Publication number Publication date
TW544903B (en) 2003-08-01
WO2002095817A2 (en) 2002-11-28
DE10124774A1 (en) 2002-12-12
CN100461356C (en) 2009-02-11
DE10124774B4 (en) 2016-05-25
CN1539163A (en) 2004-10-20

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