CN1539163A - Semiconductor component with at least one semiconductor chip on base chip serving as substrate and method for production thereof - Google Patents

Semiconductor component with at least one semiconductor chip on base chip serving as substrate and method for production thereof Download PDF

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Publication number
CN1539163A
CN1539163A CNA028103963A CN02810396A CN1539163A CN 1539163 A CN1539163 A CN 1539163A CN A028103963 A CNA028103963 A CN A028103963A CN 02810396 A CN02810396 A CN 02810396A CN 1539163 A CN1539163 A CN 1539163A
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chip
semiconductor
semiconductor chip
base chip
base
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CN100461356C (en
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H
H·休纳
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

According to the invention, a semiconductor component, with at least one semiconductor chip on a base chip serving as substrate has contact surfaces made of metal on the at least one semiconductor chip and the base chip. The semiconductor chip and the base chip are thus arranged relative to each other such that the corresponding contact surfaces of the at least one semiconductor chip and the base chip are facing each other and the facing electrical contacts are electrically connected to each other. The separation between a contact surface of the at least one semiconductor chip and the corresponding contact surface of the base chip is less than 10 [micro]m. the base chip comprises components produced by a first technique, whilst the at least one semiconductor chip comprises components produced by means of a second technique.

Description

At the semiconductor subassembly of useing at least one semiconductor chip of tool on the base chip of substrate as and make the method for this assembly
At the semiconductor subassembly of useing at least one semiconductor chip of tool on the base chip of substrate as, the present invention also is the method about the semiconductor subassembly of making this kind form about a kind of in the present invention system.
Many semiconductor subassemblies comprise circuit block, and these circuit blocks must be manufactured with different technologies, and for example, logical circuit and main memory circuit merge, and logical circuit must use the manufacture method with the memory chip of simple structure.Similarly situation is applied under the situation of power switch and the merging of its driver.The semiconductor subassembly of this kind form is installed as two encapsulated integrated circuits that are adjacent to each other on substrate, wherein comprising first of chip as internal memory, yet, another integrated circuit comprises all component of driver, the electrical connection of integrated circuit is carried out via substrate, yet, reach the method step of the suitable big figure of needs quite greatly to carry out its manufacturing based on the semiconductor subassembly of this principle manufacturing.
Perhaps, known to all circuit units that will form with single semiconductor substrate, though all circuit units of integration need space slightly in the semiconductor subassembly of semiconductor substrate, it is for complicated that carry out and make expensive.
The object of the invention is to stipulate at least two semiconductor subassemblies by the functional circuit of different technologies manufacturing of a kind of tool, and reaches the simple as far as possible whole purpose that reaches not expensive combination.And, make the semiconductor subassembly of this kind form, it can similarly be used in the same manner, method stipulated.
This purpose can reach by the feature of claim 1 and 12.Indivedual favourable details can be learnt by interdependent claim.
The present invention proposes at the semiconductor subassembly of useing at least one semiconductor chip of tool on the base chip of substrate as, this at least one semiconductor chip and this base chip tool Metal Contact zone in the case, this at least one semiconductor chip is aimed in one way about this base chip in the case, and this mode is connected to each other in the conductivity mode through specifying contact area to face with each other and should facing the zone alternately alternately for this at least one semiconductor chip and this base chip.In the case, the distance between the contact area of indivedual contact areas of this at least one semiconductor chip and this base chip of being attached thereto is less than 10 microns.A kind of not expensive and be possible by containing also by the base chip of the assembly of the first technology manufacturing in the semiconductor subassembly of making, and this at least one semiconductor chip contains the assembly by the manufacturing of second technology.
The present invention thereby propose a kind of semiconductor subassembly, wherein semiconductor chip is with two layer stacks, this combination is enough to contain the prevailing application that needs different technologies, and according to the present invention, this at least one semiconductor chip and this base chip are direct each other " face-to-face " contact.So the essential contact between these two integrated circuits can be undertaken by one step.
If necessary, many semiconductor chips also can be installed and be contacted with this base chip, then then another ground arrangement on this base chip of this semiconductor chip.
In preferable detail, this base chip is than this semiconductor chip or the bigger surface area content of these many semiconductor chip tools.In the case, be provided in the zone of this base chip that is not capped with the outside contact assembly that contacts of this semiconductor subassembly.This contact assembly can be formed as binding pad, and they can then be used to cohere the corresponding contact assembly of this semiconductor subassembly in substrate via cohering electric wire, and this semiconductor subassembly installing thereon.
According to the present invention, this base chip tool contact assembly only, on the contrary, this semiconductor chip that is installed in this base chip is this kind of tool contact assembly not, is established to extraneous electrically contacting by this base chip and contact assembly thereof.This at least one semiconductor chip that is installed in this base chip not fact of any contact assembly of tool makes that this semiconductor chip can be very little by what manufacture, and this makes that the area utilization that significantly is increased on the wafer is possible.In addition, exempt each integrated circuit individual package be provided as possibility, the integrated circuit that contacts with each other can be received in single encapsulation.
Provide the surface area content of this contact assembly of outside contact to be preferably surface area content greater than this contact area, be electrically connected by this this base chip and this at least one semiconductor chip, the result, the adaptation of the area of this semiconductor subassembly and volume is used and is guaranteed, because of only quite few contact assembly must be provided in this base chip.Because of this semiconductor chip and this semiconductor chip each other " face-to-face " and contact, very little contact area can be provided for this.
The idea according to the present invention, this base chip comprise the structure that area is concentrated, yet this at least one semiconductor chip comprises complicated logical construction.This base chip comprises the more not assembly of expensive technique manufacturing, because of the low ratio of the every wafer of this base chip in the case not for so conclusive.This base chip can comprise as switch, ESD structure, bus line, test circuit, inductor and similar object thereof.Its result represents active, the intelligent substrate of a kind of installing this semiconductor chip thereon, and this base chip is preferably the less metal level of tool as far as possible, so that simply reach the not expensive possibility that is fabricated to.
On the contrary, this semiconductor chip comprises the complicated logical construction and the metal level of tool greater number.Therefore plant form semiconductor chip be fabricated to more complicatedly, and the result be more expensive, hope makes that these semiconductor chips are as far as possible little.Can be reached by this expectation of this semiconductor subassembly that is proposed.
Further develop in the present invention, this at least one semiconductor chip can be ground to thin, and this produces the semiconductor subassembly of suitable total height.
In another details, provide this semiconductor chip with two or more multi-layered chip stack form, this chip stack is preferably with tridimensional integrated system and forms, this allows the integrated circuit of high complexity to be implemented with quite little volume.Can be with the formed chip stack of three-dimensional space integrated system by forming as WQ 96/01497, this file is also narrated the manufacture method of the chip stack of this kind form.
Electricity between this integrated circuit and mechanical connection can be by diffusion-solder technology＜SOLID〉method reaches, and it is that itself is known.Use this kind interconnection technique, the distance that is less than 10 microns can be reached.Under the situation of preferred embodiment, it is one medium-sized that this distance only is at most, or only be more preferred from 1/4th big.2 microns typical range between this contact area, and high simultaneously contact density result can be reached.
For reaching connection at this whole surface area, except contact area, this at least one semiconductor chip is connected to this base chip or except this Metal Contact zone with sticking together, also improve a kind of further metallic region, it is soldered to a kind of further metallic region of opposite placement in the same procedure step, in this step, this contact area also is connected to another in the conductivity mode, and this can taking place through stipulating method by diffusion-welding.The result, the conductivity between this contact area connect resulted from this at least one semiconductor chip and in this base chip and simultaneously correspondingly be connected that this further metallic region＜it is provided for mechanical connection at first between produced, also can understand this further metallic region and serve as extra electric work energy, this further metallic region can be followed and is used as extra electric wiring layer.Under the situation of continuous further metallic region, it can serve as the function of screen between the electronic building brick of this base chip and this at least one semiconductor chip, this make its can the plain mode uncoupling at the assembly of integrated circuit connected to one another.
Except diffusion-welding flux layer, indivedual contact areas of this at least one semiconductor chip and this base chip also can electrically contact to provide by the soldered ball connection.In the case, in this at least one semiconductor chip and this base chip, be preferably tool one packed layer by this contact area and/or the occupied zone of this further metallic region outward, so that the extra mechanical stability of this combination to be provided, this packed layer is known as " the filling primer ".
The method of the above semiconductor subassembly constructed in accordance comprises the following steps:
At wafer layer, this contact area is individually produced on this semiconductor chip and this base chip.At next step, this semiconductor chip, it is installed in integrated circuit on this base chip for those, is individually separated with this wafer combination.Then, at least one semiconductor chip in each base chip contacts in one way, this mode make this at least one semiconductor chip and this base chip alternately through specifying contact area facing with each other and should be mutual being connected to each other in the conductivity mode in the face of contact area.Afterwards, the combination that comprises this at least one semiconductor chip and this base chip is individually separated with this wafer combination.All pre-treatment step as the deposition of different metal layer, by its structuring of little shadow or the like, are not then expensively carried out with the wafer method.After carrying out above-described method step, place another this integrated circuit of arranging above packed or directly to be installed on the substrate with one.
In the case the generation of this contact area comprise a series of through the using of structured metal layer, but these metal levels comprise adhesion layer, diffusion impervious layer and weld metal layers.But being preferably with sputter or electrochemistry, this weld metal layers strengthens being applied, contact is preferably by impose a contact pressure at weld period with this semiconductor chip in this base chip and contacts, and preferably is used for this purpose in the diffusion-welding method that begins to mention.
The more accurate narration of the example of semiconductor subassembly constructed in accordance with following graphic be that the basis is provided, wherein:
Fig. 1 shows the first example specific embodiment of the semiconductor subassembly according to the present invention,
Fig. 2 a be presented at before semiconductor chip in base chip contacts according to the present invention the second example specific embodiment according to the present invention of semiconductor subassembly,
Fig. 2 b shows the another kind of structure by this base chip of Fig. 2 a,
Fig. 3 is presented at contact area and metal assembly during the distinct methods step to the using of this base chip,
Fig. 4 is presented at during the distinct methods step contact area to the second example specific embodiment of using of this base chip,
Fig. 5 shows that contact area and metal assembly to the 3rd example specific embodiment of using of this base chip, reach
Fig. 6 shows contact area and further metal assembly the 4th example specific embodiment of using to this base chip.
Fig. 1 shows the first example specific embodiment of the semiconductor subassembly according to the present invention with the cross section section.A kind of semiconductor chip 20 is installed on a kind of base chip 10, and this base chip 10 and this semiconductor chip 20 are all had a contact area.This semiconductor chip 20 is aimed to this base chip in one way and is made alternately through specifying contact area to face with each other and be connected to each other in the conductivity mode.Produce in Fig. 1 with through being electrically connected by soldered ball 30 of appointment contact area, these soldered balls systems are being soldered to these contact areas between indivedual contact areas and in each situation.For reaching bigger mechanical robustness, intermediate space is filled with packed layer 31.
As can be by the good finding of Fig. 1, this base chip be much larger than this semiconductor chip 20, and this base chip is preferably by more not expensive technique manufacturing, because of the low ratio of the every wafer of this base chip in the case not for so conclusive.For example, but this base chip switch package, ESD structure, bus, test circuit and inductor.With the same side of this semiconductor chip 20, contact assembly 12 is installed on this base chip 10, in the cross-sectional area segment table of Fig. 1 shows, only a contact assembly 12 is visible, this contact assembly 12 manufactured far beyond this contact area for big and be used as and carry out contacting with the outside of this semiconductor subassembly, for example, link electric wire and can be linked to this contact assembly 12.
The semiconductor subassembly tool is by the advantage than any big contact assembly of these semiconductor chip 20 unnecessary tools of expensive technique manufacturing according to the present invention, this allows this semiconductor chip 20 of special zonule to be reached, and this causes the increase of the area utilization on wafer.As can be by Fig. 1 finding, this semiconductor chip 20 is also unnecessary being packaged in the encapsulation before electrically contacting with this base chip 10, this contact for " face-to-face ".After contacting of this base chip and 20 of this semiconductor chips set up, can understand and it goes without saying that with encapsulation around this assembly as shown in Figure 1, this combination also can mechanically be connected directly to substrate.
Fig. 2 a is characterized in that the good especially and not expensive method of electricity and mechanical connection with the second example specific embodiment of cross section section demonstration semiconductor subassembly according to the present invention.Should electricity in this example of the 2nd figure and mechanical connection by diffusion-welding method＜SOLID method undertaken, this method is described in down.
A series of surfaces that are applied to this base chip 10 and this semiconductor chip 20 through structured metal layer, but these metal levels comprise a series of adhesion layer, diffusion impervious layer and weld metal layers, for example, 10 to 100 thick TiW＜titanium-tungsten of rice how〉layer and 1000 to the 2000 thick Cu＜copper of rice how〉layer can be provided.In the case, the character of this TiW laminated and diffusion impervious layer and adhesion layer is used to strengthen by sputter or electric current and be carried out.Consider because of integral body is clear, only the result with these layers of this contact area 11,21 forms is shown in Fig. 2 a.This contact area 11,21 contacts with indivedual contact pins 14,24 via plated-through-hole 15,25, it is respectively the assembly part of the top metal level of this base chip 10 or this semiconductor chip 20, and, thin welding flux layer, its by as 500 to 1000 how rice thick and by tin＜Sn formed, be deposited on wherein one of these these contact areas 11 or 21, these welding flux layers are necessary for thin so that forming mutually and can't used up in this adjacent metal of this diffusion-weld period.
For contacting, this semiconductor chip 20 and this base chip 10 are placed in another top, and their contact area 11,21 is relevant to each other and is adjusted, and then are soldered to each other.This is preferably and imposes 3 crust of a contact pressure＜for example〉carry out.This reaches good especially connection.
With with the same way as of this contact area 11,21, further metallic region 13,23 is made respectively on this base chip and this semiconductor chip 20.This further metallic region 13,23 mainly is used as by increasing the surface size that will weld to improve its mechanical connection between these two integrated circuits.Yet, also can understand this further metallic region 13,23 of use as extra electrical ties layer.
The advantage of this method of attachment is obviously found out by above narration.Mechanical Contact 10 of this semiconductor chip 20 and this base chip is almost carried out on whole surface area, except this further metallic region of this contact area 11,21 is used as extra join domain.Except bigger mechanical strength, they guarantee the heat conduction that improves, this further metallic region can be used on the one hand to carry out extra electric work energy＜binder couse 〉, but on the other hand by the formation that on whole surface area, is provided as far as possible with the circuit block of uncoupling in this semiconductor chip 20 and this base chip 10.Only contact with the outside of this semiconductor subassembly and to carry out via this base chip.No longer need any bonding pad by this semiconductor chip 20 than the expensive technique manufacturing, this reaches the remarkable increase that area utilizes, particularly under the situation of the little chip section of this semiconductor chip 20.In addition, providing of encapsulation no longer is necessary.
This semiconductor chip and this base chip 10 only need little surface area, because of with indivedual upper metal zone＜be respectively contact pins 14 and 24 to contact not be that known face of weld by being of a size of 100 * 100 microns squares carries out, but undertaken by little plated-through-hole 15,25.Their tools are corresponding to the surface area of front end plated-through-hole, and area requirements in the case is rough 1 * 1 micron square.These plated-through-holes can be like this little because of they during the wafer manufacturing for opening.After method during, the only not expensive little shadow of contact need be used.
20 of this base chip 10 and this semiconductor chips " face-to-face " contact and allow the entire chip area of this semiconductor chip 20 almost to be used to the number of contact area of mechanical fixation-no matter.If contact system uses soldered ball to carry out, these can be used for mechanical connection separately.Use that providing of further metallic region that solder flux protuberance contacts can cause in the top metal level space requirement increase-this is contact pins 14 and 24 metal levels of being arranged.
Compare with the use of soldered ball, when diffusion-welding method was used, this contact area 11,21 can relative to each other higher density be placed, and the average distance between two contact areas only needs 30 microns, allow every square centimeter to surpass 10,000 contact points and be implemented.
Should " face-to-face " contact the short access path also be provided at 20 of this base chip 10 and this semiconductor chips, the result, the short signal delivery time, the less stray capacitance of little distribution of pulses and connection line is possible, the electricity needs of the power driver that this minimizing may provide.What they can be manufactured as a result is littler, further reduces at the thermogenetic of this chip area and circuit.Fact expression so closely coupled to each other only provides the ESD structure also for enough on this base chip on this base chip and this semiconductor chip function.
As mentioned above, contact system with the outside of this semiconductor subassembly and be carried out via this contact assembly 12, in the example specific embodiment shown in Fig. 2 a, this contact pins 12a is placed in the top metal level with this contact pins 14 identical bits standards.When this contact area 11 and this metallic region 13 were applied, this contact assembly 12a can not be capped, and during pre-processing, this contact assembly 12a through opening is necessary for and is not capped.
Perhaps, this contact assembly 12 also is formed in the mode corresponding to this contact area 11 or this metallic region 13, the result, and this contact assembly 12 also is placed on the main side of this base chip 10.The contact that is relevant to the top metal level 12a of this base chip is then undertaken by plated-through-hole 15 equally.Under the situation of this variation, it is by Fig. 2 b representative, and the space requirement of this contact assembly 12 greatly reduces.
Fig. 3 is presented at the contact area 11 of two these base chip 10 of different phase of this method and the generation of metallic region 13 with the cross section section.Starting point is the wafer of finishing through processing, wherein to this top metal level＜that is this contact pins 14 this plated-through-hole 15 for finishing unlatching.As first step, barrier layer 17 and metal level 18 are deposited on whole surface by sputter and/or electro-deposition, after this in the rear metal level＜that is contact area 11 or metallic region 13 little shadow of position photoresist 33 use.At next step, it is represented by the figure on the right side, and by etching off, can be undertaken by wet-chemical ground by this etching in the zone that is not covered by this photoresist 33 for this metal level 18.In the case, cross and to cut by corresponding shielding nargin compensation, this represents that little shadow step must be meticulous than final structure, perhaps, electric paste etching can be performed, if uneven tropism suitably, that is does not need the expansion of structure.
Fig. 4 shows further possibility method, and wherein this contact area 11 and this metallic region 13 can be applied by electro-deposition.A kind of barrier layer, it is by being formed as TiW, Ti/TiN alloy or Ta/TaN alloy, and how meter thick copper kind crystal layer 19 is by the whole surface area of sputter in the active sides of this base chip 10 to reach about 100.This then is negative little shadow, its expression isolated groove after a while, and these are by these photoresist plate 33 expressions.Then, in the zone of 33 on this photoresist wall with copper spontaneously fill＜as representative on Fig. 4 right side.Next step removes for this photoresist 33, and at the section that this photoresist plate 33 is placed, by etching off, this can be by the execution of wet-chemical ground or by the electric paste etching method in further step for this kind crystal layer 19 and this barrier layer 17.
The little shadow of this step tool does not need the advantage of any nargin, and structure is correctly made again.Approach little shadow and also can be used except contacting little shadow, being known that, this makes that cost of shielding can be saved and the method reliability can be increased.As a result the latter for more accurate and because of low cost also be preferred methods.
For contacting between this base chip and this semiconductor chip, welding flux layer must additionally be applied to one or other this contact area.This welding flux layer must this photoresist 33 remove front or rearly be applied by electrochemical step, if this welding flux layer is applied before the removing of this photoresist 33, is known as photoresist and peels off, the solder alloy of Sn/Pb or Sn/Al alloy can be used.
The third method of using this contact area 11 and further metallic region 13 is marked by Fig. 5.This barrier layer 17 and this metal level 18 shield 34 1 via the little shadow of a kind of x-ray and follow a ground by sputter or thermal vapor deposition, for reaching this purpose, the little shadow shielding of x-ray tool plate 35, it is placed on the position of isolated groove institute desire placement after a while, and this barrier layer 17 should be by sputter because can obtain preferable sticking together.Under the situation of the method, must guarantee small distance 10 of the shielding 34 of the little shadow of this x-ray and this base chip.And, must be guaranteed through enough alignings of atomizing material.
The 4th variation of this mode, wherein the mode that produced of this contact area 11 and further metallic region 13 is shown in Fig. 6.This photoresist shielding 33, it covers isolated groove after a while, is resulted from this base chip 10.The shielding of this photoresist is answered the overlapping photoresist edge of tool or was born and cut flank, and this can be by the suitable dosage that exposes to the open air, two-layer photoresist technology or reached by the upper surface of this photoresist of sclerosis.This metal level 17,18 then is deposited by sputter and thermal evaporation, and partly the shielding at photoresist of layer of going up growth in this photoresist shielding divests the time limit by flush away in the case.Method based on Fig. 6 narration is known as " emission ".
During the sputter of little shadow shielding and during launching technique via the x-ray, this solder alloy also can be produced, because of this metal level 17,18 is applied above another with suitable thickness one, if during carrying out the method after a while that contacts between this semiconductor chip and this base chip, their then jointly participate in forming mutually, and are mixed together place like this and carry out.
During the using of this photoresist shielding 33, this barrier layer also can be applied to whole surface area earlier, the zone that after this photoresist shielding 33 removes, can be positioned at this barrier layer 17 of this isolated groove must follow quilt subsequently wet-chemical or be removed by electric paste etching.
Based on many examples narrated graphic, only semiconductor chip 20 is applied to base chip 10 in these figure.One follows a ground uses many semiconductor chips 20 in base chip 10 also within the scope of the present invention, this semiconductor chip 20 can quilt, but it is nonessential, at their rear side by thinning, the rear side thinning can be carried out by grinding operation, after this semiconductor chip 20 had been applied to this base chip 10, this semiconductor chip 20 also can be formed two or more multi-layered chip stack, and this chip stack can form by tridimensional integrated system.Reference list
10 base chip
11 contact areas
12 contact assemblies
13 metallic region
14 contact pins
15 plated-through-holes
16 isolated grooves
17 barrier layers
18 metal levels
19 kinds of crystal layers
20 semiconductor chips
21 contact areas
22
23 metallic region
24 contact pins
25 plated-through-holes
26 isolated grooves
30 soldered balls
31 packed layers
32 soldered balls
33 photoresists
The little shadow shielding of 34 x-rays
35 plates

Claims (14)

1. useing the semiconductor subassembly that the base chip of substrate (10) goes up at least one semiconductor chip of tool (20) as, wherein
-this at least one semiconductor chip (20) and this base chip (10) tool gold
Belong to contact area (11,21),
-this at least one semiconductor chip is right in one way about this base chip
Standard, this mode be this at least one semiconductor chip and this base chip alternately through referring to
Decide that contact area faces with each other and should be mutual connect each other in the conductivity mode in the face of the zone
Connect,
-reach with it at indivedual contact areas of this at least one semiconductor chip (20)
Distance between the contact area (11) of this base chip (10) that connects is less than 10
Micron,
-this base chip comprises the assembly that contains by the first technology manufacturing, and
-this at least one semiconductor chip comprises the assembly by the second technology manufacturing.
2. according to the semiconductor subassembly of claim 1, wherein this base chip (10) is provided in the zone of this base chip that is not capped with the outside contact assembly (12) that contacts of this semiconductor subassembly than this semiconductor chip (20) or the bigger surface area content of these many semiconductor chip tools.
3. according to the semiconductor subassembly of claim 1 or 2, wherein the surface area content of this contact assembly (12) is big than this contact area (11,21).
4. according to semiconductor subassembly arbitrary in the claim 1 to 3, wherein this base chip (10) comprises the structure that area is concentrated.
5. according to semiconductor subassembly arbitrary in the claim 1 to 4, wherein this at least one semiconductor chip (20) comprises complicated logical construction.
6. according to semiconductor subassembly arbitrary in the claim 1 to 5, wherein this at least one semiconductor chip (20) is ground to approaching.
7. according to semiconductor subassembly arbitrary in the claim 1 to 6, wherein this semiconductor chip (20) is a kind of two or more multi-layered chip stack, and this chip stack system forms with tridimensional integrated system.
8. according to semiconductor subassembly arbitrary in the claim 1 to 7, wherein this at least one semiconductor chip (20) and the further metallic region of this base chip (10) tool (13,23), it is placed relative to one another and the indivedual contact areas (11,21) of tool are big surface area content, and these further metallic region are to be connected to each other forever.
9. semiconductor subassembly according to Claim 8, wherein this further metallic region (13,23) is to be connected to each other forever by solder flux (32).
10. the semiconductor subassembly arbitrary according to claim 1 to 7, wherein to electrically contact be to produce by soldered ball (30) to this between indivedual contact areas (11,21) of this at least one semiconductor chip (20) and this base chip (10).
11. the semiconductor subassembly arbitrary according to claim 1 to 10, wherein between this at least one semiconductor chip (20) and this base chip (10), by this contact area (11,21) and/or the occupied outer a kind of packed layer (31) that exists in zone of this further metallic region (13,23).
12. according to the manufacture method of the arbitrary semiconductor subassembly of claim 1 to 11, wherein
-at this wafer layer, this contact area (11,21; 13,230 by indivedual
Generation is gone up at this semiconductor chip (20) and this base chip (10) in ground,
-this semiconductor chip (200 are individually separated with this wafer combination,
-at least one semiconductor chip (20) of each base chip (10) with
A kind of mode contacts, feasible this at least one semiconductor chip of this mode and this basis core
Sheet alternately through specifying contact area (11,21; 13,23) face with each other and should
It is mutual in the face of contact area is connected to each other in the conductivity mode,
-this contact area (11,21; 13, generation 23) comprises a series of warps
Using of structured metal layer, these metal levels comprise an adhesion layer, a diffusion barrier
But a retaining layer and a weld metal layers, and
-comprise this at least one semiconductor chip (20) and this base chip (10)
This combination individually separated with this wafer.
13., but should using of weld metal layers (18) be to be undertaken wherein by sputter or electric current enhancing according to the method for claim 12.
14., wherein undertaken by imposing a contact pressure at weld period with the system that contacts at this semiconductor chip of this base chip according to the method for claim 12 or 13.
CNB028103963A 2001-05-21 2002-05-17 Semiconductor component with at least one semiconductor chip on base chip serving as substrate and method for production thereof Expired - Fee Related CN100461356C (en)

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